Semiconductor Metallization Patterning via Homogeneous Etching

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Solution Overview

Problem

Current methods for patterning metallization layers on semiconductor workpieces, such as Ti/NiV/Ag stacks, are limited by electrical shorts and chip damage, restricting layer thickness to around 1 μm and requiring mechanical sawing during dicing, which is not suitable for modern dicing methods like plasma or stealth dicing.

Innovation Solution

A method involving wet and dry chemical etching processes to pattern metallization layer stacks with different materials, using an etching solution with a substantially same etching rate for layers like Ag and NiV, allowing for layer thicknesses greater than 1 μm and enabling damage-free singulation using the patterned metal back side as a mask for further processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If mechanical sawing is used during dicing to pattern metallization layers, then chip damage is prevented, but modern dicing methods like plasma or stealth dicing cannot be used

Engineering Contradiction:
Improvecompatibility with modern dicing methodsVSAvoidchip damage prevention
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The metallization layer stack is patterned before the dicing process using wet etching with an etching solution that has substantially the same etching rate for different metal layers. This preliminary patterning creates a protective mask structure that enables subsequent damage-free dicing using modern plasma or stealth dicing methods without requiring mechanical sawing

Inventive Principle:
Principle #10Preliminary action

2Reliability

If metallization layer thickness is increased to improve electrical connection reliability, then electrical shorts occur and chip damage increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidelectrical shorts and chip damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent uses an etching solution with specifically tuned parameters (substantially the same etching rate for different metal layers) to enable precise patterning of thick metallization layer stacks. This parameter optimization allows achieving reliable electrical connections with thicker layers while preventing electrical shorts and chip damage through controlled etching processes

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If different etching rates are used for different metal layers, then selective patterning is achieved, but process complexity increases

Engineering Contradiction:
Improveselective patterning precisionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent employs an etching solution that exhibits substantially the same etching rate for different metal layers (such as Ag and NiV). This homogeneous etching behavior simplifies the patterning process by eliminating the need for multiple selective etching steps, reducing process complexity while maintaining manufacturing precision through single-step patterning of the entire metallization layer stack

Inventive Principle:
Principle #33Homogeneity

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables reliable patterning of metallization layers up to several micrometers thick, preventing electrical shorts and chip damage, and allows for the use of advanced dicing techniques like plasma dicing, improving yield and process flexibility.

Implementation Method 1

patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material

Methodology Applied
Scientific EffectWet etching:

Data Source

PatentUS9293371B2Method for processing a semiconductor workpiece with metallization
Publication Date: 2016.03.22 INFINEON TECHNOLOGIES AG
  • US9293371B2 patent drawing
  • US9293371B2 patent drawing
  • US9293371B2 patent drawing

AI summary

A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.