Semiconductor Metallization via Self-Assembled Monolayers
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Solution Overview
Problem
Current semiconductor metallization methods introduce significant damage and defects in metal structures and dielectric layers during the formation of vias and trenches, particularly at the 7nm node technology and beyond, due to incomplete filling and etching-induced damages.
Innovation Solution
The method employs strategically placed selective self-assembled monolayers (SAMs) combined with sacrificial layers for bottom-up filling of vias and trenches, allowing for controlled metal growth and minimizing defects, and replaces sacrificial layers with low-k dielectric layers to avoid damage to the dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metallization methods are used to form vias and trenches, then metal structures can be created, but significant damage and defects are introduced in the metal structures and dielectric layers
Solution Approach 1:
The patent applies preliminary action by depositing self-assembled monolayers (SAMs) on the sidewalls of vias and trenches before the metal filling process. These SAMs serve as protective coatings that prevent damage to the dielectric layers during subsequent etching and filling operations, thereby resolving the contradiction between creating metal structures and avoiding damage to dielectric layers.
Solution Approach 2:
The patent uses self-assembled monolayers (SAMs) as intermediary substances between the metal filling process and the dielectric layers. These SAMs act as mediators that facilitate controlled metal deposition while protecting the underlying dielectric structures from damage, thus improving metal structure quality without compromising dielectric integrity.
2Ease of manufacture
If filling proceeds from the side-walls of vias and trenches, then metal structures can be formed, but defects are unavoidable at the junction of the growth fronts
Solution Approach 1:
The patent applies inversion by reversing the conventional filling approach. Instead of allowing metal to grow upward from the sidewalls (bottom-up), the method deposits metal in a top-down manner through the via/trench openings. This inverted approach eliminates the formation of growth front junctions that cause defects, while maintaining ease of manufacture through controlled deposition processes.
Solution Approach 2:
The patent extracts the problematic sidewall growth mechanism from the filling process. By removing the sidewall-dependent growth approach and replacing it with direct top-down deposition, the method eliminates the inherent defects at growth front junctions while preserving the manufacturability of the metal filling process.
3Manufacturing precision
If plasma etching is used to form vias and trenches, then narrow features can be created, but etching-induced damages occur in the dielectric material
Solution Approach 1:
The patent applies beforehand cushioning by depositing self-assembled monolayers (SAMs) on the dielectric surfaces before plasma etching operations. These SAMs act as protective cushioning layers that absorb etching damage, allowing precise formation of narrow vias and trenches while minimizing damage to the surrounding dielectric material.
Solution Approach 2:
The patent uses self-assembled monolayers (SAMs) as intermediary protective layers between the plasma etching process and the dielectric material. These intermediaries enable precise etching of narrow features while shielding the dielectric from harmful etching effects, thus resolving the contradiction between dimensional accuracy and damage prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and damage in metal structures and dielectric layers, enabling efficient bottom-up filling of narrow features with minimal voids and etching-induced damage, thereby improving the reliability and efficiency of semiconductor metallization processes.
Implementation Method 1
Applying a self-assembled monolayer selectively on the exposed metal surface
Implementation Method 2
Growing a metal on the self-assembled monolayer so as to fill the at least one through-hole
Data Source
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AI summary
A method for fabricating a semiconductor device, comprising: a. Providing a structure comprising a first sacrificial layer (2) comprising at least one through-hole exposing a metal (4) surface and optionally an oxide (5) surface, b. Applying a self-assembled monolayer (10) selectively on the exposed metal (4) surface and/or on the oxide (5) surface, c. Growing a metal (9) on the self-assembled monolayer (10) and on the exposed metal (4) surface if no self-assembled monolayer (10) is present thereon, so as to fill the at least one through-hole, thereby forming at least one metal (9) structure, d. Replacing the first sacrificial layer (2) by a replacement dielectric layer (11) having a dielectric constant of at most 3.9.