Semiconductor Metallization with Varying Thickness and Width

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Solution Overview

Problem

Current semiconductor technologies face challenges in creating metallization with varying thickness and widths, requiring new methods for efficient fabrication of semiconductor structures.

Innovation Solution

The method involves forming a dielectric barrier layer over a workpiece, creating openings, depositing a seed layer, and electroplating fill layers to achieve metallization levels with specific thickness and width configurations, allowing for the formation of semiconductor structures with multiple metal lines of different dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional metallization methods are used, then fabrication process is simple, but inability to create metallization with varying thickness and widths

Engineering Contradiction:
Improvemetallization thickness and width variationVSAvoidfabrication process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The metallization layer is divided into multiple segments with different thicknesses and widths by forming openings in the dielectric barrier layer at specific locations. Each opening allows selective electroplating to create metal lines with customized dimensions, enabling varying metallization characteristics across different regions of the semiconductor structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the metallization layer are given different local properties through selective opening formation and electroplating. Each opening location receives tailored electroplating treatment to achieve the desired thickness and width for that specific area, allowing local optimization of electrical and mechanical properties.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If multiple electroplating steps are performed, then metallization with varying dimensions is achieved, but manufacturing process time increases

Engineering Contradiction:
Improvemetallization thickness and width controlVSAvoidfabrication process time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The dielectric barrier layer with pre-formed openings is created before the electroplating process. This preliminary structuring defines the exact locations and dimensions of future metallization features, allowing subsequent electroplating steps to proceed efficiently with precise dimensional control without requiring multiple iterative adjustments.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dielectric barrier layer serves as an intermediary structure that controls and mediates the electroplating process. By incorporating openings in the barrier layer, it directs the electroplating material to specific locations and thicknesses, enabling precise metallization formation while streamlining the overall manufacturing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the creation of semiconductor structures with metallization levels that include multiple metal lines of varying thickness and width, addressing the need for flexible and precise metallization in semiconductor chips and integrated circuits.

Implementation Method 1

electroplating fill layers to achieve metallization levels with specific thickness and width configurations

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9230885B2Semiconductor structure and method for making same
Publication Date: 2016.01.05 INFINEON TECHNOLOGIES AG
  • US9230885B2 patent drawing
  • US9230885B2 patent drawing
  • US9230885B2 patent drawing

AI summary

One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.