Semiconductor Integrated Circuit Microstrip Line Design
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Solution Overview
Problem
Conventional semiconductor integrated circuit devices using nitride semiconductors face challenges in reducing chip area and enhancing heat dissipation, particularly due to the difficulty in processing sapphire substrates and the complexity of fabrication processes, which limits their application in submillimeter wave bands.
Innovation Solution
A semiconductor integrated circuit device is designed with a microstrip line formed by interconnections through through holes in the semiconductor layer and insulating film, allowing for reduced chip area and improved heat dissipation by separating the semiconductor layer from the crystal growth substrate and using a supporting substrate with excellent heat dissipation properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a coplanar line is used with ground lines on the surface of the chip, then the fabrication process is simpler, but the chip area cannot be reduced
Solution Approach 1:
The patent transitions from a two-dimensional coplanar configuration to a three-dimensional microstrip structure by forming ground lines on the back surface of the substrate and signal lines on the front surface, connected through via holes. This dimensional change enables significant chip area reduction while maintaining electrical performance.
2Area of moving object
If via holes are formed in sapphire substrates to create microstrip lines, then chip area is reduced, but the fabrication process becomes difficult or impossible
Solution Approach 1:
The patent divides the via hole formation process into two separate stages: first forming via holes in the semiconductor layer, then forming additional via holes in the substrate after the semiconductor layer has been processed. This segmentation allows each etching step to be optimized independently, making the overall process feasible.
Solution Approach 2:
The patent performs preliminary actions by forming the first set of via holes in the semiconductor layer before substrate processing, and preparing the semiconductor layer structure in advance. This preliminary preparation simplifies subsequent substrate via hole formation and enables microstrip line creation without making the overall fabrication process impossible.
3Reliability
If sapphire substrate is used for crystal growth, then crystal quality is good, but heat dissipation is poor
Solution Approach 1:
The patent extracts the semiconductor layer from the sapphire substrate after crystal growth is complete. This separation removes the poor heat dissipation characteristic of sapphire while preserving the high-quality crystal structure that was grown on the sapphire substrate. The extracted semiconductor layer can then be mounted on substrates with better thermal properties.
4Temperature
If the semiconductor layer is separated from the crystal growth substrate, then heat dissipation is enhanced, but the fabrication process becomes more complex
Solution Approach 1:
The patent segments the fabrication process into distinct phases: crystal growth on sapphire, semiconductor layer processing and via hole formation, substrate removal, and final mounting. This segmentation manages the complexity by organizing multiple steps into logical sequences, making the overall process controllable and manufacturable despite the increased number of steps.
Data Source
AI summary
A semiconductor integrated circuit device includes: a semiconductor layer having a principal surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; an insulating film formed in contact with the semiconductor layer and having a second through hole; a first interconnection formed on the semiconductor layer through the first through hole and connected to one of the source electrode, the drain electrode and the gate electrode which is exposed in the first through hole; and a second interconnection formed on the insulating film through the second through hole and connected to another of the source electrode, the drain electrode and the gate electrode which is exposed in the second through hole. The first interconnection and the second interconnection face each other and form a microstrip line.