Semiconductor Package Mirror Mode Pin Assignment
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Solution Overview
Problem
Conventional memory device packages with mirrored pin assignments on opposite sides of a PCB require longer traces, leading to increased electrical resistance and timing skew due to reversed pin arrangements, which degrade signal quality.
Innovation Solution
Implementing a switch circuit that allows memory device packages to operate in either normal or mirror mode, enabling pin assignments to be mirrored, thus allowing for shorter, more balanced trace lengths and reduced complexity in trace layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory device packages are mounted on opposite sides of PCB with mirrored pin assignments, then footprint area is reduced, but trace length increases causing higher electrical resistance and timing skew
Solution Approach 1:
The patent inverts the conventional pin assignment arrangement by implementing mirror mode operation. When the lower memory device package is flipped upside down, instead of having address pins in reverse order, the pin assignments are mirrored so that corresponding address pins (A[2], A[8], A[7], A[9]) align vertically. This inversion allows traces to connect corresponding pins directly across the PCB thickness via vias, dramatically reducing trace length while maintaining the reduced footprint benefit of opposite-side mounting.
Solution Approach 2:
The patent transitions the trace routing from a lateral planar path to a vertical three-dimensional path through the PCB. By using vias to connect corresponding address pins between opposite sides of the PCB, the trace routing moves from horizontal traces across the board surface to vertical traces through the board thickness. This dimensional change significantly reduces the effective trace length for address signals while maintaining electrical connectivity.
2Reliability
If traces are made shorter to reduce electrical resistance, then signal quality improves, but trace layout complexity increases
Solution Approach 1:
The patent introduces asymmetry in the pin assignment configuration through mirror mode operation. The lower memory device package uses a mirrored pin assignment where address pins are reassigned to different physical locations compared to the upper package. This asymmetric arrangement, combined with selective enabling through control signals, allows for optimized trace routing that minimizes length for critical address traces while maintaining manufacturing feasibility and reducing overall layout complexity.
Data Source
AI summary
Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate. The first device package includes a plurality of first package contacts having a first arrangement of corresponding pin assignments, and the second device package includes a plurality of second package contacts and a switch circuit operably coupled to the second package contacts. The switch circuit is configured to receive a switch signal via the support substrate, and to assign the second package contacts to either the first arrangement of corresponding pin assignments or a second arrangement of corresponding pin assignments based on the switch signal.