Semiconductor Patterning via Misaligned Mask Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for patterning material layers in semiconductor structures, particularly in DRAM devices, are costly and time-consuming due to the need for multiple precise steps as device sizes miniaturize, leading to inefficiencies in the manufacturing process.
Innovation Solution
A method involving a two-stage lithography process and self-aligned double patterning (SADP) to form patterned material layers, where a first stack of material layers is patterned in both array and peripheral regions, with subsequent layers and masks used to create aligned and misaligned patterns to achieve high-density patterns efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional separate patterning methods are used for array and peripheral regions, then manufacturing precision can be maintained, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent merges the patterning processes for array and peripheral regions into a single unified process. By forming a common first patterned mask layer that simultaneously defines both array patterns and peripheral patterns, the method eliminates the need for separate patterning steps, thereby reducing process complexity while maintaining manufacturing precision through the self-aligned nature of the unified approach
2Manufacturing precision
If multiple precise patterning steps are used for miniaturized devices, then patterning precision is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent combines multiple patterning operations into fewer steps by using a first patterned mask layer that serves dual purposes for both array and peripheral regions. This merging of operations reduces the total number of patterning steps required, thereby improving manufacturing efficiency while maintaining the precision needed for miniaturized devices
Solution Approach 2:
The method performs preliminary patterning actions by forming the first patterned mask layer that pre-defines both array and peripheral patterns before subsequent processing steps. This preliminary action establishes the foundation for both regions simultaneously, reducing the need for additional corrective or separate patterning steps later in the process
3Manufacturing precision
If separate patterning processes are used for array and peripheral regions, then pattern alignment can be controlled, but manufacturing cost and time increase
Solution Approach 1:
The patent merges the patterning operations for array and peripheral regions into a single simultaneous process using a common first patterned mask layer. This eliminates the sequential execution of separate patterning processes, thereby reducing manufacturing cycle time while maintaining pattern alignment through the self-aligned configuration of the unified patterning approach
Data Source
AI summary
A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.