Semiconductor Package Misaligned Pads Prevent Solder Sweeping

Solution Overview

Problem

Current semiconductor packages face challenges in achieving high reliability due to the solder sweeping phenomenon during thermal compression bonding, which can lead to short circuits and contact failures, especially in the peripheral regions where pads are aligned with TSVs and bumps.

Innovation Solution

The semiconductor package design includes misaligned pads and bumps with respect to TSVs, where the pads in the peripheral region are offset from the centerline of the corresponding TSVs and bumps, allowing for sufficient accommodation of the solder layer's fluidity and reducing the risk of short circuits through asymmetrical pad design and appropriate misalignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If pads are aligned with TSVs and bumps in peripheral regions, then manufacturing precision is improved, but reliability deteriorates due to solder sweeping phenomenon causing short circuits

Engineering Contradiction:

Improvealignment precisionVSAvoidbonding reliability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The pad structure is designed with asymmetry by extending the pad beyond the centerline of the TSV in the radial direction. This asymmetric configuration allows the pad to accommodate the solder layer's fluidity during thermal compression bonding, preventing the solder from sweeping to adjacent regions and causing short circuits, thus resolving the contradiction between alignment precision and bonding reliability

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The pad is designed with different geometries in different regions: the pad extends beyond the TSV centerline in the radial direction to accommodate solder fluidity, while maintaining proper alignment in other directions. This local quality variation allows the pad to serve multiple functions - precise alignment and solder accommodation - simultaneously resolving the contradiction

Inventive Principle:

Principle #3Local quality

2Reliability

If pads are offset from TSV centerlines to accommodate solder fluidity, then reliability is improved, but manufacturing precision deteriorates due to misalignment

Engineering Contradiction:

Improvebonding reliabilityVSAvoidalignment precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The pad structure is designed with asymmetry by extending the pad beyond the centerline of the TSV in the radial direction. This asymmetric configuration allows the pad to accommodate the solder layer's fluidity during thermal compression bonding, preventing the solder from sweeping to adjacent regions and causing short circuits, thus resolving the contradiction between alignment precision and bonding reliability

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The pad is designed with different geometries in different regions: the pad extends beyond the TSV centerline in the radial direction to accommodate solder fluidity, while maintaining proper alignment in other directions. This local quality variation allows the pad to serve multiple functions - precise alignment and solder accommodation - simultaneously resolving the contradiction

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the reliability of the semiconductor package by preventing short circuits and contact failures, maintaining robust bonding despite the solder sweeping phenomenon, and optimizing the bonding force between pads and bumps.

Implementation Method 1

allowing for sufficient accommodation of the solder layer's fluidity

Methodology Applied

Scientific EffectFluidity:

Data Source

PatentUS10658300B2Semiconductor package and semiconductor device including the same

Publication Date: 2020.05.19 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.