Semiconductor Misalignment Correction via Convolution Kernel
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Solution Overview
Problem
The manufacturing process of semiconductor devices faces misalignment issues due to membrane stress and stress at material joints, which existing methods struggle to accurately correct, especially when stacking layers of different materials.
Innovation Solution
A pattern generation device and method that includes a misalignment value calculation unit and a pattern correction unit, utilizing a convolution of a layout function and an integral kernel to calculate and correct misalignment values, allowing for efficient correction of patterns across the entire surface of semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional stress simulation methods are used to calculate misalignment values, then measurement precision is improved, but device complexity and calculation time increase significantly
Solution Approach 1:
The patent extracts only the essential components needed for misalignment calculation from complex stress simulations. By formulating a dedicated misalignment value calculation unit that uses simplified convolution operations between layout functions and stress kernels, it separates the critical misalignment prediction function from the full stress simulation system, achieving accurate results with reduced complexity
Solution Approach 2:
The patent replaces complex mechanical stress simulation systems with a mathematical convolution-based calculation system. Instead of using full finite element stress analysis, it substitutes a simplified mathematical model that convolves layout functions with stress kernels to directly compute misalignment values, dramatically reducing computational complexity while maintaining precision
2Manufacturing precision
If full stress simulation is performed across the entire chip surface, then manufacturing precision is improved, but productivity decreases due to excessive calculation time
Solution Approach 1:
The patent segments the chip surface into multiple regions and processes each region independently using parallel computation. By dividing the large-scale misalignment calculation into smaller regional tasks that can be executed simultaneously, it maintains high manufacturing precision across the entire chip while significantly improving productivity through parallel processing
Solution Approach 2:
The patent performs preliminary preparation by pre-computing stress kernels and layout functions before the actual misalignment calculation. This preliminary action allows the main calculation to proceed more efficiently by using pre-processed data, reducing the overall calculation time required for full-chip pattern generation while maintaining precision
3Measurement precision
If measured values from actual devices are used to correct misalignment, then measurement precision is improved, but device complexity increases due to additional measurement and correction processes
Solution Approach 1:
The patent performs preliminary measurement and characterization of stress effects on actual devices to create accurate stress kernels. These pre-characterized kernels capture the true stress behavior of the device structure, enabling highly precise misalignment predictions in subsequent calculations without requiring complex real-time measurement and correction processes
Solution Approach 2:
The patent creates a mathematical model (stress kernel) that copies the essential stress characteristics of the actual device structure. This copied representation allows the system to predict misalignment accurately by simulating stress effects through convolution, eliminating the need for complex physical measurement and correction apparatus while maintaining high precision
Data Source
AI summary
According to the present embodiment, the pattern generation device includes a misalignment value calculation unit configured to acquire a layout information, calculate a layout function from the layout information, and calculate a misalignment value by a convolution of the layout function and an integral kernel having a predetermined parameter, and a pattern correction unit configured to correct a pattern to generate a modified layout information using a calculated result by the misalignment value calculation unit, and output the modified layout information.