Mis-alignment Detection in Semiconductor Unit Cell Blocks
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Solution Overview
Problem
As semiconductor devices, such as DRAM, undergo high integration and reduced unit cell areas, mis-alignment issues arise due to increased capacitor aspect ratios, leading to tilting or collapse, which existing technologies struggle to accurately detect and correct.
Innovation Solution
A mis-alignment detection method using a finite element method (FEM) model to calculate residual stress functions and generate a bulk layer effect (BLE) prediction algorithm, enabling accurate detection of mis-alignment in semiconductor devices by analyzing unit cell blocks and reflecting corrections on masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the unit cell area is reduced to increase integration, then the degree of integration is improved, but mis-alignment occurs due to increased capacitor aspect ratio
Solution Approach 1:
The patent applies preliminary action by pre-calculating residual stress functions using FEM models for different unit cell block sizes and generating BLE prediction algorithms before actual manufacturing. This allows mis-alignment to be predicted and compensated in advance, preventing the problem from occurring during the actual fabrication process.
Solution Approach 2:
The patent changes parameters by using FEM models to calculate residual stress functions that account for different unit cell block sizes, capacitor dimensions, and material properties. These parameter variations are input into the BLE prediction algorithm to accurately predict mis-alignment for specific device configurations.
2Quantity of substance
If the capacitor aspect ratio is increased to maintain capacitance in reduced area, then the capacitance requirement is met, but the capacitor may tilt or collapse
Solution Approach 1:
The patent replaces direct mechanical measurement of capacitor stability with a computational mechanics approach. FEM models simulate the mechanical stress and deformation of capacitors with high aspect ratios, predicting mis-alignment without requiring physical prototypes or destructive testing.
Solution Approach 2:
The patent introduces residual stress functions and BLE prediction algorithms as intermediaries between the capacitor design parameters and the actual mis-alignment measurement. These mathematical models act as mediators that translate geometric and material parameters into predicted mis-alignment values.
3Ease of operation
If existing detection methods are used, then the detection process is simple, but the detection accuracy is insufficient
Solution Approach 1:
The patent creates a virtual copy of the unit cell block through FEM modeling. This digital twin allows accurate prediction of mis-alignment by simulating the physical behavior of the capacitor structure under various conditions, providing measurement precision that exceeds direct physical measurement methods.
Solution Approach 2:
The patent segments the detection problem into distinct computational steps: generating FEM models for different unit cell configurations, calculating residual stress functions for each configuration, and applying the appropriate BLE prediction algorithm. This segmentation allows complex predictions to be made through a systematic process.
Data Source
AI summary
The inventive concepts provide a mis-alignment (MA) detection method for a semiconductor device, the MA detection method comprising; inputting size information about a unit cell block of the semiconductor device, generating a finite element method (FEM) model based on the size information, calculating a residual stress function of the unit cell block using the FEM model, generating a bulk layer effect (BLE) prediction algorithm for the unit cell block by inputting the residual stress function into an initial BLE prediction algorithm generated based on a main cell block of the semiconductor device, and selectively detecting the MA of the unit cell block using the BLE prediction algorithm.