Semiconductor Chip Mounting with Mixed Conductivity Bonding
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Solution Overview
Problem
Semiconductor devices with multiple chips face reliability issues due to inadequate bonding and insulation methods, leading to potential electrical connections and reduced miniaturization capabilities.
Innovation Solution
A semiconductor device design featuring a resin sealing type configuration with a conductive chip mounting portion, using a conductive bonding member for one chip and an insulating bonding member for another, ensuring proper electrical connection and insulation between chips, and utilizing a common die pad for both chips to enhance reliability and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common die pad is used for multiple semiconductor chips, then device complexity and manufacturing cost are reduced, but reliability deteriorates due to potential electrical connections between chips
Solution Approach 1:
The patent applies local quality by using different bonding members with different properties at different locations. Specifically, a first bonding member with insulation property is used for the first semiconductor chip, while a second bonding member with conductivity is used for the second semiconductor chip. This local differentiation allows the common die pad structure to maintain both electrical insulation where needed and electrical connection where needed, resolving the reliability concern while preserving the simplified common die pad architecture.
2Reliability
If bonding members are used to mount chips, then electrical connection and insulation are achieved, but device complexity increases due to additional components
Solution Approach 1:
The patent applies universality by making the bonding members serve multiple functions. The first bonding member provides both mechanical mounting and electrical insulation, while the second bonding member provides both mechanical mounting and electrical connection. This multi-functionality reduces the need for separate components, thereby maintaining reliability while avoiding excessive increase in device complexity.
3Area of stationary object
If semiconductor chips are adjacently arranged and packaged, then miniaturization is achieved, but reliability deteriorates due to inadequate bonding and insulation methods
Solution Approach 1:
The patent applies local quality by differentiating the bonding members based on the specific electrical requirements of each chip location. The first bonding member is designed with insulation properties for the first chip, while the second bonding member is designed with conductive properties for the second chip. This localized differentiation enables compact adjacent arrangement of chips while maintaining high reliability through appropriate bonding and insulation at each specific location.
Data Source
AI summary
In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.