Semiconductor Patterning with Mixed Pitch Regions
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Solution Overview
Problem
The existing self-aligned double patterning (SADP) technique requires additional time and effort to design and correct the peripheral circuit region in semiconductor devices, especially when forming patterns with small pitches, as it is more complicated compared to cell regions.
Innovation Solution
A method involving the formation of first and second patterns with alternating pitches, a space insulating layer with gap regions, and subsequent etching to create third patterns, using these patterns and the insulating layer as an etching mask to reduce the complexity of pattern formation in semiconductor devices, particularly in cell and peripheral circuit regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SADP is used to form patterns in the peripheral circuit region, then fine pitch patterns can be achieved, but design complexity and correction time increase significantly
Solution Approach 1:
The method segments the pattern formation process into distinct regions: cell array regions using SADP for fine pitch patterns, and peripheral circuit regions using direct patterning for larger pitches. The insulating layer is selectively removed in peripheral regions to enable direct patterning, while maintaining SADP structures in cell regions. This segmentation allows each region to use the most appropriate patterning method for its requirements.
Solution Approach 2:
The insulating layer is applied with different properties in different regions: in peripheral circuit regions, the insulating layer is selectively removed to enable direct patterning with larger pitches, while in cell array regions, the insulating layer remains to maintain SADP structures for fine pitch patterns. This local differentiation allows optimal pattern formation in each region type.
2Manufacturing precision
If SADP is used to form patterns in the peripheral circuit region, then fine pitch patterns can be achieved, but additional correction time and effort are required
Solution Approach 1:
The method segments the pattern formation process into distinct regions: cell array regions using SADP for fine pitch patterns, and peripheral circuit regions using direct patterning for larger pitches. The insulating layer is selectively removed in peripheral regions to enable direct patterning, while maintaining SADP structures in cell regions. This segmentation allows each region to use the most appropriate patterning method for its requirements.
Solution Approach 2:
The insulating layer is formed and selectively removed in advance during the patterning process, preparing the peripheral circuit regions for direct patterning before the final pattern formation step. This preliminary preparation eliminates the need for subsequent design corrections and re-analysis, saving time in the later stages of device fabrication.
3Manufacturing precision
If patterns with different pitches are formed in different regions, then integration density can be optimized, but pattern connectivity between regions becomes complex
Solution Approach 1:
The insulating layer serves as an intermediary element that facilitates connectivity between regions with different pitch patterns. By selectively removing the insulating layer in peripheral circuit regions while maintaining it in cell array regions, the method enables direct patterning in peripheral regions that can connect to SADP-formed patterns in cell regions, simplifying the connectivity interface between different pitch domains.
Data Source
AI summary
Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.