Semiconductor Module Asymmetric Bonding for Switching Balance
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Solution Overview
Problem
In IGBT power semiconductor modules, current imbalances due to distorted gate signals during turn-on can lead to slower switching times for some IGBTs, reducing the short circuit safe operating area, and uneven temperature distribution can exacerbate these issues.
Innovation Solution
A semiconductor module design with a substrate plate featuring semiconductor switch and diode chips connected via bond wires, where an additional emitter current path is inductively coupled with the gate current path to equalize voltage drops across chips, improving thermal and electromagnetic coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are arranged symmetrically to equalize current paths, then gate signal distortion is reduced, but temperature distribution becomes uneven
Solution Approach 1:
The patent applies asymmetry by intentionally creating different current path lengths for different IGBT chips. The emitter conductor is designed with varying distances to each chip, and bond wire lengths are deliberately different, creating asymmetric electrical paths that compensate for thermal differences while maintaining reliable switching operation.
2Temperature
If chips are distributed homogeneously to improve temperature distribution, then thermal behavior improves, but current path lengths become different causing gate signal distortion
Solution Approach 1:
The patent applies local quality by designing each IGBT chip's electrical connection path with specific local characteristics. Each chip has its own optimized bond wire configuration and emitter conductor connection point, allowing each location to be tailored for its specific thermal and electrical requirements rather than using a uniform approach.
Solution Approach 2:
The patent changes electrical parameters (bond wire lengths, emitter conductor connection positions) to compensate for thermal parameter variations. By adjusting these electrical parameters locally for each chip, the system achieves both homogeneous temperature distribution and balanced gate signals despite the heterogeneous chip distribution.
3Ease of manufacture
If bond wire lengths are equalized, then manufacturing is simplified, but gate current paths experience different inductive voltage drops
Solution Approach 1:
The patent deliberately changes the bond wire length parameter for each IGBT chip to compensate for differences in emitter path inductance. This parameter adjustment ensures that the total gate current path inductance is equalized across all chips, maintaining gate signal integrity while requiring precise control of wire bonding parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances thermal behavior and balances electromagnetic coupling, ensuring consistent switching behavior across semiconductor switch chips and improving the module's current rating and safe operating area.
Implementation Method 1
an additional emitter current path is inductively coupled with a gate current path
Data Source
AI summary
A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate, wherein the diode chip is electrically connected antiparallel to the semiconductor switch chip; wherein the semiconductor switch chip is electrically connected via bond wires to an emitter conductor on the substrate plate providing a first emitter current path, which emitter conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; wherein a gate electrode of the semiconductor switch chip is electrically connected via a bond wire to a gate conductor on the substrate plate providing a gate current path, which gate conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; and wherein a protruding area of the emitter conductor runs besides the diode chip towards the first semiconductor switch chip and the first semiconductor switch chip is directly connected via a bond wire with the protruding area providing an additional emitter current path running at least partially along the gate current path. The semiconductor switch chip is a first semiconductor switch chip and the diode chip is a first diode chip, which are arranged in a first row. The semiconductor module comprises further a second row of a second semiconductor switch chip and a second diode chip attached to the collector conductor, wherein the diode chip of each row is electrically connected antiparallel to the semiconductor switch chip of the same row and the first and second rows are electrically connected in parallel. The first semiconductor switch chip is arranged besides the second diode chip and the second semiconductor chip is arranged besides the first diode chip.