Symmetrical Semiconductor Module Layout for Balanced Current Paths
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Solution Overview
Problem
Power semiconductor module arrangements face challenges in minimizing unequal current density distribution, electrical losses, and thermal stress, while optimizing substrate size and symmetry for efficient performance.
Innovation Solution
The semiconductor module arrangement features multiple substrates with symmetrical layouts and configurations, including identical second and third substrates connected to a third node, ensuring identical voltage and current transfer characteristics across various current paths, and utilizing different semiconductor bodies for heat management and efficient cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple substrates are used to reduce current density inequality, then current distribution improves, but device complexity increases
Solution Approach 1:
The power semiconductor module divides the semiconductor arrangement into multiple substrates (first substrate, second substrate, third substrate), each carrying specific semiconductor bodies. This segmentation allows current paths to be distributed across multiple substrates, reducing current density inequality on each individual substrate while maintaining overall system reliability.
Solution Approach 2:
The patent employs symmetrical layout designs where the second substrate and third substrate have equal layouts, creating balanced current paths. This symmetry ensures that current densities are evenly distributed across identical substrates, preventing unequal current distribution while managing the complexity through standardized repeated structures.
2Stability of the object's composition
If symmetrical layout is implemented across substrates, then thermal stress distribution improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements symmetrical layouts where the second substrate and third substrate are designed with equal configurations. This symmetry ensures that thermal stresses are distributed evenly across the module, preventing localized thermal accumulation. The standardized symmetrical design actually reduces manufacturing precision requirements by providing repeatable patterns that are easier to manufacture consistently.
Solution Approach 2:
The patent standardizes key layout parameters (trace widths, spacing, component placement) across the symmetrical substrates. By defining and maintaining these parameters consistently, the design achieves uniform thermal stress distribution while simplifying manufacturing through parameter standardization rather than requiring high precision for each individual variation.
3Area of stationary object
If substrate size is minimized, then device compactness improves, but electrical losses increase
Solution Approach 1:
By dividing the semiconductor arrangement across multiple substrates, the patent reduces the area required on each individual substrate while maintaining adequate current path lengths. This segmentation allows current to flow through multiple substrates in series, preserving electrical performance despite smaller individual substrate areas, thereby reducing overall electrical losses.
Solution Approach 2:
The patent extends current paths into the third dimension by routing current across multiple stacked or adjacent substrates. This dimensional approach allows compact substrate areas while maintaining sufficient current path lengths, as the current travels through multiple layers or positions rather than requiring long paths on a single large substrate.
Data Source
AI summary
A semiconductor module arrangement includes a first substrate with a first plurality of semiconductor bodies arranged thereon, a second substrate with a second plurality of semiconductor bodies arranged thereon, and a third substrate with a third plurality of semiconductor bodies arranged thereon. The first, second and third pluralities of semiconductor bodies together form a semiconductor arrangement, the semiconductor arrangement including a first node configured to be operatively coupled to a first electrical potential, and a second node configured to be operatively coupled to a second electrical potential that is different from the first electrical potential. A layout of the third substrate with the third plurality of semiconductor bodies arranged thereon equals a layout of the second substrate with the second plurality of semiconductor bodies arranged thereon. The first substrate is configured to be connected to the first node and the second node, and each of the second substrate and the third substrate is configured to be connected to a third node. A first current path extending between the first node and the third node via the first substrate and the second substrate provides identical voltage and current transfer characteristics as a second current path extending between the first node and the third node via the first substrate and the third substrate, and a third current path extending between the second node and the third node via the first substrate and the second substrate provides identical voltage and current transfer characteristics as a fourth current path extending between the second node and the third node via the first substrate and the third substrate.