Semiconductor Module Lamination for High-Voltage Chip Embedding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current chip embedding processes fail to meet high voltage application requirements due to limitations in breakdown voltage, ion impurity levels, and adhesion issues with polymer layers, particularly for peak voltages above 650V, leading to reliability concerns and potential delamination.
Innovation Solution
A method for fabricating semiconductor device modules involves providing a core layer with an opening, disposing a semiconductor device, and applying encapsulant layers with a B-stage compound or mold compound, which are then laminated together to ensure proper adhesion and embedding of the semiconductor device, using materials like FR1, FR2, or BT-epoxy, and incorporating thermal conductive fillers for improved heat dissipation and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current PCB materials and chip embedding processes are used, then manufacturing simplicity is maintained, but reliability deteriorates due to insufficient breakdown voltage and ion impurity levels for high voltage applications
Solution Approach 1:
The patent uses composite encapsulant materials consisting of epoxy resin combined with specific fillers (such as alumina, silica, or boron nitride) to achieve both high breakdown voltage and good thermal conductivity. This composite approach allows the material to simultaneously provide electrical insulation, thermal management, and mechanical protection, resolving the contradiction between reliability and ease of manufacture.
Solution Approach 2:
The patent modifies the chemical and physical parameters of the encapsulant material by adjusting the epoxy resin formulation, adding cross-linking agents, and incorporating functional fillers. These parameter changes enable the material to withstand higher voltages and temperatures while maintaining manufacturability through standard encapsulation processes.
2Reliability
If polymer layers like prepreg layers are used for chip embedding, then ease of manufacture is improved, but adhesion deteriorates leading to local delamination
Solution Approach 1:
The patent applies different surface treatments to specific regions of the encapsulant and substrate surfaces. Plasma treatment or chemical etching is applied locally to enhance adhesion at the interface between the encapsulant and the PCB, while the bulk material maintains its original properties. This localized quality enhancement improves adhesion without complicating the overall manufacturing process.
Solution Approach 2:
The patent introduces adhesion promoters or coupling agents as intermediary layers between the encapsulant and the substrate. These intermediary materials chemically bond to both surfaces, creating a strong interface that prevents delamination while allowing the use of standard polymer-based encapsulants and manufacturing processes.
3Temperature
If standard encapsulation materials are used, then ease of manufacture is maintained, but thermal management deteriorates due to insufficient heat dissipation
Solution Approach 1:
The patent incorporates porous filler materials such as alumina or boron nitride particles with controlled pore structures into the encapsulant. These porous materials provide both thermal conductivity pathways and electrical insulation, enabling effective heat dissipation while maintaining the ease of manufacture through conventional mixing and molding processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and adhesion of semiconductor device modules, enabling them to handle higher voltages by improving the structural integrity and thermal management, thus addressing the limitations of existing technologies.
Implementation Method 1
laminating together the first and second encapsulant layers and the encapsulant
Implementation Method 2
incorporating thermal conductive fillers for improved heat dissipation and structural integrity
Data Source
Figure 1~2B
Figure 2C~3
Figure 4A~4D
AI summary
A method (100) for fabricating a semiconductor device module, the method comprising providing a first encapsulant layer and a core layer disposed on the first encapsulant layer wherein the core layer comprises an opening (110), disposing a semiconductor device in the opening, the semiconductor device comprising a die carrier and a semiconductor die disposed on the die carrier (120), dispensing an encapsulant onto the semiconductor device (130), applying a second polymer layer onto the encapsulant so that the encapsulant is pressed into the opening (140); and laminating together the first and second encapsulant layers and the encapsulant (150).