Semiconductor Module Layout for Thermal Spacing and Chip Testing
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Solution Overview
Problem
Power semiconductor module arrangements face challenges with large size due to thermal requirements, high costs, and difficulty in testing individual semiconductor elements, which are often not separately packaged.
Innovation Solution
The semiconductor module arrangement includes pre-packaged semiconductor components with metallic layers attached to electrodes and a dielectrically insulating layer, allowing for separate testing and improved thermal properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor elements are mounted directly on substrate metallization layers, then electrical connection is achieved, but thermal requirements force large distances between elements increasing module size
Solution Approach 1:
The patent segments the substrate into multiple electrically isolated regions, each capable of carrying semiconductor elements. By dividing the substrate into isolated zones with independent electrical potentials, the design allows elements to be placed closer together without thermal interference, as each region can be independently thermally managed.
Solution Approach 2:
The patent introduces an intermediary layer structure between semiconductor elements and the substrate metallization. This intermediary system includes dielectric layers and conductive patterns that mediate both electrical connection and thermal management, allowing elements to be mounted closer while maintaining thermal performance through the intermediary thermal pathways.
2Ease of manufacture
If individual semiconductor elements are not separately packaged, then manufacturing is simplified, but testing of individual elements becomes difficult or impossible
Solution Approach 1:
The patent assigns each semiconductor element to its own isolated electrical region on the substrate. This segmentation creates independent test zones where individual elements can be electrically accessed and tested through dedicated connection structures, enabling post-assembly testing without requiring separate packaging of each element.
Solution Approach 2:
The substrate structure serves multiple functions simultaneously: it provides mechanical support, electrical connection, thermal management, and individual element accessibility for testing. The universal substrate design integrates all these functions, eliminating the need for separate packaging while enabling comprehensive testing capabilities.
3Reliability
If large distances are maintained between semiconductor elements, then thermal requirements are met, but overall module size increases and costs increase
Solution Approach 1:
By segmenting the substrate into electrically isolated regions, the patent enables dense packing of semiconductor elements. Each segmented region can be independently thermally managed, allowing elements to be placed closer together while maintaining thermal performance through the isolated region boundaries that prevent thermal interference.
Solution Approach 2:
The patent changes the electrical and thermal parameters of the substrate by introducing multiple isolated regions with different electrical potentials and thermal characteristics. This parameter differentiation allows optimized thermal management at the regional level, enabling closer element spacing while maintaining overall thermal performance through localized parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces overall size, enhances thermal performance, and enables easy testing of individual components, increasing yield and reducing costs.
Implementation Method 1
a first metallic layer (202, 206) attached to the first electrode (201, 205) of the semiconductor chip (20) by means of an electrically conducting connection layer (208), a second metallic layer (204) attached to the second electrode (203) of the semiconductor chip (20) by means of an electrically conducting connection layer (208)
Implementation Method 2
a dielectrically insulating layer (210) covering surfaces of the semiconductor chip (20), wherein surfaces of the first and second metallic layers (202, 204) that face away from the semiconductor chip (20) are not covered by the dielectrically insulating layer (210)
Data Source
Figure 1~3
Figure 4A~6
Figure 7~9
AI summary
A semiconductor module arrangement comprises a substrate, and at least one semiconductor component arranged on the substrate. Each of the at least one semiconductor component comprises a semiconductor chip having a first and a second electrode, a first metallic layer attached to the first electrode of the semiconductor chip by means of an electrically conducting connection layer, a second metallic layer attached to the second electrode of the semiconductor chip by means of an electrically conducting connection layer, and a dielectrically insulating layer covering surfaces of the semiconductor chip, wherein surfaces of the first and second metallic layers that face away from the semiconductor chip are not covered by the dielectrically insulating layer.