Semiconductor Module Layout With Separated Control Wiring

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Solution Overview

Problem

The existing semiconductor modules are bulky and costly due to the integration of main wiring and signal wiring on the same substrate, which necessitates heat dissipation measures for large currents while being unnecessary for signal lines, hindering miniaturization.

Innovation Solution

A semiconductor module design featuring a multilayer substrate with separate control boards for control wiring mounted on metal plates, utilizing the space efficiently and reducing the size of the module by separating control boards from the main wiring layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If main wiring and signal wiring are integrated on the same substrate, then electrical connection is simplified, but module size increases and cost increases due to heat dissipation requirements

Engineering Contradiction:
Improvewiring integration complexityVSAvoidmodule size
Core Design Contradiction:
Device complexityVSVolume of moving object

Solution Approach 1:

The patent divides the wiring system into two separate substrates: a first substrate for main wiring (power supply and output terminals) and a second substrate for signal wiring (control signals). This segmentation allows each substrate to be optimized independently - the first substrate handles high-current power transmission without heat dissipation constraints, while the second substrate handles low-current control signals with compact routing, thereby reducing overall module size while maintaining wiring functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a two-dimensional planar integration of all wiring on a single substrate to a three-dimensional stacked configuration where the first and second substrates are positioned at different vertical levels. The control board mounts the second substrate on its rear surface, creating a multi-layer structure that separates power wiring and signal wiring in the vertical dimension, enabling compact space utilization without thermal interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If main wiring and signal wiring are integrated on the same substrate, then manufacturing is simplified, but substrate cost increases due to heat dissipation measures

Engineering Contradiction:
Improvewiring manufacturing simplicityVSAvoidsubstrate configuration complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent segments the wiring manufacturing into two independent processes: manufacturing the first substrate with main wiring patterns for power transmission, and manufacturing the second substrate with signal wiring patterns for control signals. Each substrate can be manufactured using appropriate materials and processes optimized for its specific function, avoiding the need for expensive heat dissipation structures in the signal substrate while maintaining manufacturing simplicity through modular assembly.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different quality requirements to different regions of the wiring system: the first substrate uses thick copper foils and robust construction for high-current power transmission, while the second substrate uses standard thin-film wiring techniques suitable for low-current control signals. This local optimization of material properties and manufacturing quality reduces overall substrate cost while maintaining appropriate performance for each wiring function.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12469826B2Semiconductor module
Publication Date: 2025.11.11 FUJI ELECTRIC CO LTD
  • US12469826B2 patent drawing
  • US12469826B2 patent drawing
  • US12469826B2 patent drawing

AI summary

A semiconductor module includes a multilayer substrate having a main wiring layer formed therein, a main current flowing in the main wiring layer when the semiconductor device is turned on, a first and second semiconductor elements, each of which has a top electrode on a top surface thereof and a bottom electrode on a bottom surface thereof, and is disposed on a top surface of the main wiring layer to which the bottom electrode is conductively connected, a metal plate having an end portion, a bottom surface of the end portion being conductively connected to the top electrode of the first semiconductor element, and a control board including an insulating plate disposed on the top surface of the end portion and a control wiring layer disposed on a top surface of the insulating plate for controlling turning on and off of the first and second semiconductor elements.