Semiconductor Module Corrugated Interconnect Noise Attenuation
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Solution Overview
Problem
In semiconductor modules, parallel connection of IGBT and FRD elements leads to multiple current loops with independent resonance frequencies, causing noise resonance that can negatively affect gate control of the IGBT due to matching of resonance and oscillation frequencies.
Innovation Solution
A semiconductor module design featuring a corrugated surface on the interconnect layers to attenuate high-frequency noise, disrupting the coincidence between oscillation frequency of the IGBT noise and parallel resonance frequency of the circuit, thereby suppressing noise oscillation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If IGBT and FRD elements are connected in parallel to achieve high breakdown voltage and high current, then power handling capability is improved, but multiple current loops are formed causing noise resonance that can negatively affect gate control
Solution Approach 1:
The patent introduces a damping resistor specifically designed to convert the harmful noise resonance into beneficial energy dissipation. The resistor is connected in parallel with the IGBT element, and its resistance value is carefully selected to provide damping effect at the resonant frequency, thereby converting the harmful oscillation into useful energy dissipation that protects the gate control circuit
2Reliability
If a damping resistor is connected in parallel with the IGBT element to suppress noise resonance, then gate control stability is improved, but power loss increases
Solution Approach 1:
The patent optimizes the resistance value of the damping resistor to achieve the best balance between noise suppression and power loss. By carefully selecting the resistance value based on the resonant frequency and circuit parameters, the damping effect is maximized while minimizing the power dissipation, thus achieving parameter optimization
3Object-affected harmful factors
If the resistance value of the damping resistor is increased to enhance damping effect, then noise suppression is improved, but voltage drop across the resistor increases
Solution Approach 1:
The patent determines the optimal resistance value by analyzing the resonant frequency and circuit characteristics. The resistance is set to provide sufficient damping at the resonant frequency while keeping the voltage drop within acceptable limits during normal operation, achieving a balanced parameter selection
4Object-affected harmful factors
If the damping resistor is positioned closer to the IGBT element to reduce inductance, then damping effectiveness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by mounting the damping resistor on the reverse surface of the substrate, directly opposing the IGBT element. This three-dimensional arrangement minimizes the loop inductance and enhances damping effectiveness while maintaining a compact and manufacturable structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The corrugated surface effectively attenuates the S21 parameter, reducing the likelihood of noise resonance and protecting the IGBT from damage by ensuring that the oscillation frequency of the noise signal no longer matches the parallel resonance frequency of the circuit.
Implementation Method 1
a corrugated surface on the interconnect layer or the other interconnect layer includes a corrugated surface on the other interconnect layer
Implementation Method 2
The second interconnect layer includes a corrugated surface on the second interconnect layer or the first interconnect layer includes a corrugated surface on the first interconnect layer
Data Source
AI summary
According to one embodiment, a semiconductor module includes: a substrate; a first interconnect layer provided on the substrate; a plurality of first semiconductor elements provided on the first interconnect layer, each of the first semiconductor elements having a first electrode, a second electrode, and a third electrode, and the second electrode being electrically connected to the first interconnect layer; a plurality of first rectifying elements provided on the first interconnect layer, each of the first rectifying elements having a fourth electrode and a fifth electrode, and the fifth electrode being electrically connected to the first interconnect layer; and a second interconnect layer provided on the substrate, and the second interconnect layer being electrically connected to the first electrode and the fourth electrode. The second interconnect layer includes a corrugated surface or the first interconnect layer includes a corrugated surface.