Power Semiconductor Module Terminal Layout for Accurate Current Sensing
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Solution Overview
Problem
The existing power semiconductor modules face challenges in miniaturization due to the need for increased inductance in the main current path for accurate current measurement, which requires longer metal layers or additional bonding wires, leading to increased module size and potential decreases in measurement accuracy due to temperature changes.
Innovation Solution
The power semiconductor module design incorporates a detection terminal configuration where a portion of the main terminal functions as the inductor, allowing for increased inductance without the need for additional metal layers or bonding wires, facilitating miniaturization and reducing temperature-induced inductance changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the length of the metal layer on the insulating substrate is increased to increase inductance, then the inductance increases, but the size of the power semiconductor module becomes large
Solution Approach 1:
The patent merges the main terminal and detection terminal functions by configuring the detection terminal to share part of the metal layer with the main terminal. The detection terminal includes a first terminal connected to the main terminal and a second terminal connected to the insulating substrate, allowing the same metal layer to serve both as a current carrier and an inductance element for detection, thereby eliminating the need for separate dedicated detection structures and reducing overall module size while maintaining adequate inductance for accurate current measurement
2Measurement precision
If additional metal layers or bonding wires are provided to increase inductance, then the inductance increases, but the device complexity increases
Solution Approach 1:
The patent applies multi-functionality by designing the detection terminal structure to perform multiple functions: the first terminal of the detection terminal serves as both a current detection point and part of the inductance path, while also being electrically connected to the main terminal. This universal design allows the existing metal layers to serve dual purposes as both power/ground paths and detection paths, eliminating the need for additional dedicated inductance structures and reducing device complexity
3Measurement precision
If the length of the bonding wire is increased to increase inductance, then the inductance increases, but the module size becomes large
Solution Approach 1:
The patent extracts the inductance function from the bonding wire and relocates it to the metal layer structure on the insulating substrate. By forming the detection terminal directly on the insulating substrate using the existing metal layers, the design eliminates the need for long bonding wires to create inductance, thereby reducing the overall module size while maintaining the necessary inductance value for accurate current measurement through voltage integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the miniaturization of the power semiconductor module while maintaining accurate current measurement and reducing the impact of temperature changes on measurement accuracy.
Implementation Method 1
an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer
Implementation Method 2
an inductor being provided in a main current path between a first end of the first main terminal and a second end of the first main terminal
Data Source
AI summary
A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.