Semiconductor Embedded Module Dual-Layer Insulator Via Formation

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Solution Overview

Problem

The challenge in semiconductor embedded modules is the difficulty in forming vias with high precision due to downsizing and reduced pitch, which can lead to damage to the circuit or wiring of the semiconductor device during the via formation process.

Innovation Solution

A semiconductor embedded module structure is proposed, featuring a first insulating layer with a lower grinding rate and a second insulating layer with a higher grinding rate, where the second layer is used to form vias on the external connection pads, protecting the semiconductor device from damage even if the via formation position is slightly dislocated.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single insulating layer is used, then the structure is simple, but the circuit or wiring of the semiconductor device may be damaged during via formation due to positioning dislocation

Engineering Contradiction:

Improveprotection of circuit and wiringVSAvoidinsulating layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The single insulating layer is divided into two separate insulating layers: a first insulating layer with low grinding rate that protects the semiconductor device, and a second insulating layer with high grinding rate that is removed during via formation. This segmentation allows the protective function to be separated from the via formation function, solving the contradiction between reliability and complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first insulating layer acts as an intermediary protective layer between the semiconductor device and the via formation process. It mediates the conflict by providing protection during via formation while allowing the second insulating layer to be selectively removed for via access.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If via formation is performed directly on the insulating layer, then the process is simple, but positioning precision deteriorates due to downsizing and reduced pitch

Engineering Contradiction:

Improvevia formation precisionVSAvoidvia formation process

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The first insulating layer is formed in advance before via formation, creating a protective barrier that compensates for potential positioning errors during the subsequent via formation process. This preliminary protective action allows for more tolerant via formation processes while maintaining precision.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If the grinding rate is increased for faster via formation, then productivity improves, but the risk of damaging the semiconductor device increases

Engineering Contradiction:

Improvevia formation speedVSAvoidsemiconductor device integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Different regions of the insulating structure have different grinding rates: the second insulating layer has a high grinding rate for fast via formation, while the first insulating layer has a low grinding rate to protect the semiconductor device. This local differentiation of material properties resolves the contradiction between productivity and reliability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The grinding rate parameter is changed by using different insulating layer materials with distinctly different grinding characteristics. The second layer uses high-grind-rate material for speed, while the first layer uses low-grind-rate material for protection, allowing both high productivity and high reliability.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This structure effectively prevents damage to the semiconductor device's circuit and internal wiring during via formation, allowing reliable external connection without harming the semiconductor device, suitable for high-density, thin, and compact electronic equipment.

Implementation Method 1

a second insulating layer which is provided on the first insulating layer and which has a grinding rate larger than that of the first insulating layer

Methodology Applied

Scientific EffectGrinding: Abrasion

Data Source

PatentUS8742589B2Semiconductor embedded module and method for producing the same

Publication Date: 2014.06.03 TDK CORP

AI summary

A semiconductor embedded module 1 of the present invention has a configuration in which a semiconductor device 20, which is an electronic component such as a semiconductor IC (die) in a bare chip state, is embedded in a resin layer 10 (second insulating layer). In the semiconductor device 20, a redistribution layer 22 is connected to land electrodes. A protective layer 24 (first insulating layer) is provided on the redistribution layer 22, and is provided with openings such that external connection pads P of the redistribution layer 22 are exposed. Also, the resin layer 10 is formed to cover the protective layer 24, and vias V are formed at the positions of the respective external connection pads P of the redistribution layer 22. The grinding rate of the resin layer 10 is larger than that of the protective layer 24.