Semiconductor Module With Dual-Read ECC Parity Recovery
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Solution Overview
Problem
As data transmission speeds increase in semiconductor devices, the probability of errors occurring during data transmission also rises, necessitating improved methods to ensure data reliability, particularly in systems using error correction codes like ECC.
Innovation Solution
A semiconductor module that includes an address control circuit, memory circuits, and an ECC circuit to generate and utilize internal addresses and decoding enable signals to correct errors in data by using meta data stored as parity bits after a read operation, enhancing the error correction capability of the ECC circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve productivity, then the probability of errors during data transmission increases, worsening data reliability
Solution Approach 1:
The patent applies preliminary action by performing a first read operation to obtain initial data and parity information before the actual write operation. The ECC circuit uses this pre-obtained parity information to perform error correction on the data before it is written back to the memory device, thereby preventing error propagation while maintaining high transmission speeds.
Solution Approach 2:
The patent introduces an intermediary ECC (Error Correction Code) circuit that acts as a mediator between the memory device and the data transmission channel. This intermediary performs error detection and correction operations on data during transmission, allowing high-speed data transfer while maintaining data reliability through intermediate error correction processing.
2Reliability
If error correction capability is enhanced by using additional parity bits and multiple read operations, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the memory device to perform multiple functions using the same hardware resources. The memory device can perform both normal data read/write operations and error correction operations using the same memory cells and circuitry, depending on the operation mode. The first and second read operations use the same memory structure but serve different purposes: initial data retrieval and error correction data retrieval.
Solution Approach 2:
The patent merges the error correction function with the existing memory read/write operations. Instead of adding a completely separate error correction subsystem, the error correction is integrated into the memory operation flow by utilizing the same memory structure for both data storage and error correction code storage, and by combining multiple read operations into a unified error correction process.
Data Source
AI summary
A semiconductor module includes an address control circuit configured to generate an internal address based on an address in a first read operation and a second read operation that are sequentially performed and configured to generate multiple decoding enable signals and an error information enable signal, a memory circuit including multiple mats and configured to output internal data based on the internal address and the multiple decoding enable signals in the first read operation and configured to output internal meta data and second internal parities based on the internal address and the multiple decoding enable signals in the second read operation, and an error information storage circuit configured to output first internal parities based on the internal address and the error information enable signal in the first read operation.