Semiconductor Module Embedding Circuit Elements to Reduce Wiring Length
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Solution Overview
Problem
Conventional semiconductor modules face challenges in miniaturization due to long wiring lengths between semiconductor chips and passive components, which affect signal transmission quality and hinder module miniaturization.
Innovation Solution
A semiconductor module design featuring a wiring substrate with a semiconductor chip mounted upside-down, a resin portion between the chip and substrate, and a circuit element with terminals connected to both the substrate and chip, reducing wiring length through redistribution wiring and embedded circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If passive components are mounted two-dimensionally on the wiring substrate surface, then the wiring substrate can be simplified in structure, but the module area increases and miniaturization becomes difficult
Solution Approach 1:
The patent transitions from two-dimensional surface mounting to three-dimensional space utilization by mounting passive components in the space between the wiring substrate and semiconductor chip. This vertical arrangement reduces the horizontal area occupied while maintaining structural simplicity.
Solution Approach 2:
The patent embeds passive components within the resin sealant portion, effectively nesting them inside the encapsulation structure. This allows components to occupy internal space rather than requiring separate surface area, achieving miniaturization without increasing overall module footprint.
2Ease of manufacture
If wire bonding is used to connect the semiconductor chip to the wiring substrate, then the chip can be connected to the substrate, but the wiring length increases and signal transmission quality deteriorates
Solution Approach 1:
The patent extracts the passive components from the traditional wire bonding path and places them in the space between the chip and substrate. This removes the need for long arcuate wire bonds that extend from chip terminals to peripheral substrate connections, significantly shortening the effective wiring length for signal paths.
Solution Approach 2:
By utilizing the vertical space between chip and substrate for component placement, the patent creates direct vertical wiring paths through the resin sealant, replacing long horizontal wire bonds with shorter vertical connections that improve signal transmission quality.
3Reliability
If the wiring substrate occupies a large area to accommodate passive components with proper intervals, then component reliability is maintained, but module miniaturization is hindered
Solution Approach 1:
The patent moves passive component placement from the horizontal plane to the vertical space between chip and substrate. This dimensional transition allows components to be positioned close to the chip without requiring large horizontal intervals, maintaining reliability through proper electrical connections while minimizing substrate area.
Solution Approach 2:
Instead of expanding the substrate area outward to accommodate components, the patent inverts the approach by utilizing the internal vertical space within the encapsulation volume. This reverses the traditional expansion direction and achieves component integration without increasing footprint.
Data Source
AI summary
There is provided a semiconductor device that enables a semiconductor module that connects a wiring substrate and a semiconductor chip mounted on the wiring substrate via a circuit element and that has reduced a wiring length to improve transmission quality of signals or the like so as to achieve miniaturization of the semiconductor module. The semiconductor device includes a wiring substrate, a semiconductor chip disposed on an upper surface of the wiring substrate, a resin portion formed between the wiring substrate and the semiconductor chip, and a circuit element embedded in the resin portion. The circuit element includes a first terminal connected to wiring formed on the upper surface of the wiring substrate, and a second terminal connected to a bump provided on a lower surface of the semiconductor chip.