Semiconductor Module Gate Drive Synchronization
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Solution Overview
Problem
In semiconductor power modules, the rapid switching operation is hindered by the delayed rise and fall of signal waveforms due to parasitic inductance between the gate drive IC and the gate terminal, leading to inefficiencies in high-frequency switching operations.
Innovation Solution
A semiconductor module design featuring two independent gate drive circuits and switching devices connected in parallel or series, with a control circuit to synchronize and adjust the timing of gate drive signals, reducing parasitic inductance and enhancing switching speed by minimizing the difference in signal transmission times between the circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single gate drive circuit is used to control switching devices, then the device complexity is reduced, but the switching speed deteriorates due to parasitic inductance causing delayed rise and fall times
Solution Approach 1:
The gate drive function is segmented into multiple independent gate drive circuits, each controlling specific switching devices. This segmentation allows each circuit to drive its associated switching devices with minimal parasitic inductance, thereby improving switching speed while distributing the overall system complexity across multiple manageable units.
Solution Approach 2:
A control circuit acts as an intermediary to coordinate the timing of multiple gate drive circuits. This intermediary synchronizes the operation of parallel or series-connected switching devices, ensuring proper timing relationships while allowing each gate drive circuit to operate independently with optimized signal paths.
2Productivity
If multiple gate drive circuits are used to improve switching speed, then the switching frequency increases, but the signal transmission timing difference between circuits worsens
Solution Approach 1:
The control circuit monitors and adjusts the timing of gate drive signals from multiple gate drive circuits, using feedback mechanisms to synchronize their operation. This feedback control compensates for timing differences between parallel or series-connected switching devices, enabling high switching frequencies while maintaining precise timing relationships.
Solution Approach 2:
The system dynamically adjusts the timing of gate drive signals based on the operational state of switching devices. The control circuit modifies signal transmission timing in real-time to compensate for variations in parasitic inductance and ensure synchronized operation, allowing the system to maintain optimal performance across different switching conditions.
3Ease of operation
If the gate drive signal transmission path is extended to connect gate drive IC and gate terminal, then the ease of operation improves, but the parasitic inductance increases causing delayed rise and fall times
Solution Approach 1:
The patent optimizes the local quality of the gate drive signal transmission path by minimizing the length and impedance of connection wires between each gate drive circuit and its associated switching device gate terminal. This local optimization reduces parasitic inductance at critical interfaces while maintaining overall system operability through the coordinating control circuit.
Data Source
AI summary
A semiconductor module of an embodiment includes a first switching device, a first gate drive circuit controlling ON/OFF of the first switching device, a second switching device connected with the first switching device in parallel or in series, a second gate drive circuit controlling ON/OFF of the second switching device, and a control circuit controlling timing of transmitting a gate drive signal from the first gate drive circuit and transmitting a gate drive signal from the second gate drive circuit by synchronizing the first gate drive circuit and the second gate drive circuit.