Semiconductor Module Laminate Layout for Compact Half-Bridge Routing
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Solution Overview
Problem
Existing semiconductor power stage packages face challenges in efficiently routing signals and handling high currents due to limited space, requiring a solution that balances signal rerouting with high current handling capabilities while minimizing parasitics and optimizing layout.
Innovation Solution
A semiconductor module with a laminated structure featuring a core layer, redistribution layers, and vertically oriented transistor devices with Through Silicon Vias (TSVs) for enhanced signal and power layout, allowing for separate signal and power redistribution structures with reduced via diameters and thicker Cu layers for improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional packaging with leadframes is used for electrical interconnections, then the package can accommodate multiple semiconductor devices, but the limited space available prevents efficient routing of signals and handling of high currents
Solution Approach 1:
The patent transitions from planar leadframe-based interconnections to a three-dimensional laminated structure with multiple redistribution layers (RDLs) stacked vertically. This dimensional change allows signals and power to be routed through multiple layers, effectively increasing the available routing space without increasing the package footprint, thereby resolving the contradiction between limited package area and signal routing efficiency
Solution Approach 2:
The interconnection structure is segmented into multiple functional redistribution layers (first RDL, second RDL, third RDL) that are spatially separated and specialized. The first RDL handles power distribution, the second RDL handles signal routing, and the third RDL provides additional interconnection. This segmentation allows each layer to be optimized for its specific function, improving overall routing efficiency while maintaining compact packaging
2Device complexity
If conventional interconnection structures are used, then the package structure is simple, but parasitics increase and electrical performance deteriorates
Solution Approach 1:
By moving interconnections into the vertical dimension with multiple stacked RDLs, the patent reduces the lateral trace lengths required for signal and power routing. This dimensional reorganization minimizes loop areas and trace lengths, thereby reducing parasitic inductance and resistance without requiring a fundamentally complex interconnection architecture
Solution Approach 2:
Different redistribution layers are designed with locally optimized properties: the first RDL uses thicker copper traces for high-current power paths, while the second and third RDLs use optimized trace geometries for signal integrity. This local quality differentiation allows each region of the interconnection structure to be tailored for its specific electrical function, improving overall electrical performance without uniformly increasing complexity
3Volume of moving object
If space is optimized for compact packaging, then package size is reduced, but flexibility in signal rerouting is limited
Solution Approach 1:
The multi-layer RDL architecture provides multiple vertical pathways for signal and power routing. Signals can be routed through different combinations of RDLs and vias, providing design flexibility and adaptability for different circuit configurations. This vertical routing dimension enables compact packaging while maintaining rerouting flexibility that would be impossible in a single-plane structure
Solution Approach 2:
The redistribution layers act as intermediary structures between the semiconductor devices and the external package pins. These RDLs provide multiple intermediate routing options and connection points, allowing flexible signal paths to be established between devices while maintaining a compact overall package volume. The vias serving as vertical connectors further enable flexible three-dimensional routing
Data Source
AI summary
A method includes forming a laminate structure including an electrically insulating core layer having a first side and a second side, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side, providing a first transistor device and a second transistor device, and providing a control chip, embedding the first transistor device, the second transistor device and the control chip in the core layer, forming a half-bridge circuit that comprises the first transistor device connects to the second transistor device, wherein first sides of the control chip, and one of the first and second transistor devices face towards the first redistribution layer, wherein the second transistor device comprises one or more conductive device that electrically couple gate electrodes at the first side of the second transistor device to a pad arranged on a second side of the second transistor device.