Semiconductor Power Module Layout for Stray Inductance and Heat Dissipation
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Solution Overview
Problem
Power modules in vehicle control systems suffer from high stray inductance, poor heat dissipation, and high power consumption, leading to potential module failure and control failures due to excessive losses during frequent switching operations.
Innovation Solution
A semiconductor power device with a specific arrangement of conductive regions and power chips on a substrate, including a fourth conductive region that separates and reduces stray inductance, enhances heat dissipation, and increases power density by optimizing the layout and connections of DC and AC signal transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If power modules operate with frequent switching at high speed, then switching efficiency is improved, but switching losses increase and generate excessive heat
Solution Approach 1:
The patent segments the power module into functionally independent chip modules (rectifier bridge module, inverter module, capacitor module) that can be independently optimized and arranged. This segmentation allows for optimized current paths within each module, reducing inductance and switching losses while maintaining high switching speed capability.
Solution Approach 2:
The patent transitions from traditional planar PCB layouts to a three-dimensional stacked architecture where chip modules are vertically arranged and interconnected via substrate circuits. This dimensional change enables shorter current paths, reduced stray inductance, and improved heat dissipation, thereby reducing switching losses while maintaining high switching speeds.
2Ease of manufacture
If traditional PCB layout is used, then manufacturing is simple, but stray inductance is large and heat dissipation is poor
Solution Approach 1:
The patent replaces traditional mechanical PCB routing with integrated substrate circuits that are formed during semiconductor manufacturing processes. This substitution enables precise control of current paths, minimized inductance, and built-in heat dissipation structures, achieving both manufacturing feasibility and superior electrical/thermal performance.
Solution Approach 2:
The patent employs composite substrate structures combining conductive layers, insulating layers, and heat dissipation materials in a multi-layer configuration. This composite approach enables simultaneous optimization of electrical characteristics (low inductance) and thermal characteristics (effective heat dissipation) while maintaining manufacturing compatibility.
3Power
If compact module design is implemented, then power density increases, but heat dissipation becomes more difficult
Solution Approach 1:
The patent implements a nested modular architecture where chip modules are stacked vertically and interconnected through substrate circuits. This nesting enables compact spatial arrangement (high power density) while maintaining independent thermal management paths for each module, preventing heat accumulation despite increased compactness.
Solution Approach 2:
The substrate serves as an intermediary structure that simultaneously provides electrical interconnection and thermal management functions. The substrate's conductive layers carry currents between modules while its thermal conduction pathways conduct heat away from power-generating chips, enabling compact design without compromising heat dissipation.
Data Source
AI summary
A semiconductor power device, includes: a substrate; a first, a second, a third, and a fourth conductive regions disposed on the substrate, where the first conductive region and the second conductive region are disposed on two opposite sides of the third conductive region, the fourth conductive region is disposed between the first conductive region and the third conductive region and between the second conductive region and the third conductive region, the first, the second, and the fourth conductive regions are configured to transmit DC signals, and the third conductive region is configured to transmit AC signals; a first power chip mounted in the first conductive region and connected to the third conductive region; a second power chip mounted in the second conductive region and connected to the third conductive region; and a third power chip mounted in the third conductive region and connected to the fourth conductive region.