Semiconductor Module Terminal Layout for Parasitic Inductance Balance
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Solution Overview
Problem
There is a demand for energy-saving, sophisticated, and smaller electronic devices, which requires improving the performance and reducing the size of semiconductor modules, particularly in addressing parasitic inductance components along the main circuit current path.
Innovation Solution
A semiconductor module configuration with a conductive substrate and semiconductor elements arranged to equalize parasitic inductance components, featuring offset input and output terminals and conductive portions to minimize inductance variations, and a conducting member that connects the semiconductor elements to form a stable current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor module structure is used, then manufacturing is simpler, but parasitic inductance components along the main circuit current path are not equalized
Solution Approach 1:
The patent applies asymmetry by offsetting the input terminals and output terminals from the conductive substrate in different directions. The first input terminal and second input terminal are offset in one sense of a first direction, while the output terminal is offset in another sense of the first direction. This asymmetric arrangement equalizes the parasitic inductance components along the main circuit current path by balancing the current distribution across the semiconductor elements.
Solution Approach 2:
The patent segments the conductive substrate into a first conductive portion and a second conductive portion that are spaced apart in the first direction. The semiconductor elements are divided into first semiconductor elements bonded to the first conductive portion and second semiconductor elements bonded to the second conductive portion. This segmentation allows independent optimization of current paths and facilitates equalization of parasitic inductance components.
2Volume of moving object
If module size is reduced, then electronic devices become smaller, but parasitic inductance equalization becomes more difficult
Solution Approach 1:
The patent utilizes spatial arrangement in multiple dimensions to achieve parasitic inductance equalization in a compact form. By offsetting terminals in the first direction (perpendicular to the thickness direction) and arranging conductive portions and semiconductor elements along the second direction, the patent creates optimized current paths in two dimensions, enabling inductance equalization without increasing module volume.
3Productivity
If current distribution to semiconductor elements is unequal, then performance is reduced, but achieving equal distribution increases design complexity
Solution Approach 1:
The patent achieves equipotentiality in terms of current distribution by symmetrically arranging the first and second semiconductor elements relative to the offset terminals. The conducting members connect the semiconductor elements to the conductive portions in a balanced configuration, ensuring that parasitic inductance components are equalized and current is distributed uniformly across all semiconductor elements.
Data Source
AI summary
A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion. The semiconductor module further includes: a first conducting member connected to the first semiconductor elements and second conductive portion; and a second conducting member connected to the second semiconductor elements and second input terminal.