Semiconductor Module Layout for Parasitic Inductance Equalization
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Solution Overview
Problem
There is a need to improve the performance and reduce the size of semiconductor modules to meet the demand for energy-saving and sophisticated electronic devices, while also equalizing parasitic inductance components along the path of main circuit current.
Innovation Solution
A semiconductor module configuration with a conductive substrate and semiconductor elements arranged in a specific layout, where first and second semiconductor elements are bonded to different conductive portions, and input and output terminals are offset to form paths for main circuit current, reducing parasitic inductance components and optimizing current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor elements are arranged in a conventional layout on a supporting substrate, then the module structure is simple, but parasitic inductance components along the main circuit current path are not equalized and current distribution is uneven
Solution Approach 1:
The supporting substrate is divided into multiple conductive portions (first conductive portion and second conductive portion) that are spatially separated. Semiconductor elements are segmented into first semiconductor elements bonded to the first conductive portion and second semiconductor elements bonded to the second conductive portion. This segmentation allows independent current path optimization for each group, equalizing parasitic inductance components along different main circuit current paths while maintaining a relatively simple overall module structure.
2Volume of moving object
If semiconductor elements are placed closer together to reduce module size, then the module size decreases, but parasitic inductance equalization and current distribution become more difficult
Solution Approach 1:
The patent utilizes the vertical dimension (thickness direction) by bonding semiconductor elements to different conductive portions on the same supporting substrate plane. First semiconductor elements are bonded to the first conductive portion while second semiconductor elements are bonded to the second conductive portion, which is offset in the thickness direction. This dimensional arrangement allows compact horizontal placement while maintaining separate, optimized current paths for parasitic inductance equalization.
Data Source
AI summary
A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion. The semiconductor module further includes: a first conducting member connected to the first semiconductor elements and second conductive portion; and a second conducting member connected to the second semiconductor elements and second input terminal.