Semiconductor Module Inductance Reduction via Multi-Layer Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor modules have high inductance between PN terminals, leading to increased switching losses and terminal heating issues, particularly at higher frequencies and increased outputs.
Innovation Solution
The semiconductor module design includes a layout where the third and fourth conductive layers are disposed between the first and second conductive layers, connected to a case terminal, with semiconductor elements arranged in a mirror image configuration to reduce inductance and distribute current paths, thereby reducing heating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wiring layout is used with PN terminals, then manufacturing is simple, but inductance between terminals is high causing increased switching losses
Solution Approach 1:
The patent segments the current path by introducing multiple conductive layers (first, second, third, and fourth conductive layers) that divide the current flow into separate paths. This segmentation reduces the inductance between PN terminals by creating parallel current paths, thereby reducing switching losses while maintaining manageable complexity through systematic layering.
Solution Approach 2:
The patent transitions from a planar wiring layout to a three-dimensional multi-layer conductive structure. By stacking conductive layers vertically and connecting them through vias, the current path is optimized in the vertical dimension, reducing the loop area and inductance between PN terminals, which directly reduces switching losses.
2Temperature
If conventional terminal configuration is used, then manufacturing is easier, but terminal heating is concentrated and excessive
Solution Approach 1:
The patent segments the terminal structure by creating multiple conductive layers with distributed current paths. The first and second conductive layers connect to the P terminal while the third and fourth layers connect to the N terminal, distributing the current across multiple paths and reducing concentrated heating at any single terminal point.
Solution Approach 2:
The patent applies local quality by creating different conductive layer configurations in different regions. The conductive layers are strategically positioned to optimize current distribution in high-density areas, with varying thicknesses and patterns to manage local heat generation and improve thermal dissipation at critical terminal regions.
Data Source
AI summary
A semiconductor module includes first to fourth semiconductor elements, each having an upper-surface electrode and a lower-surface electrode, first to fourth conductive layers, each extending in a first direction and being independently disposed side by side in a second direction orthogonal to the first direction, and an output terminal connected to the second and third conductive layers. The lower-surface electrodes of each of the first to fourth semiconductor elements are respectively conductively connected to the first to fourth conductive layers. The third conductive layer and the fourth conductive layer are disposed between the first conductive layer and the second conductive layer and are connected to the output terminal to have an equal potential.