Semiconductor Module Lead Frame Surface Roughness

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Solution Overview

Problem

Conventional semiconductor modules face challenges in maintaining durability due to peeling issues between the lead frame and resin, particularly at the chip connecting portion, which is prone to thermal stress and resin cracking, despite matching linear expansion coefficients.

Innovation Solution

The semiconductor module incorporates a rough surface region on the lead frame's chip connecting portion with a developed interfacial area ratio of 0.2 or more, formed by laser irradiation or particle injection, to increase contact area and prevent peeling, and an inhibition region with concave and flat portions to inhibit solder wet-spreading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a smooth surface is used at the chip connecting portion, then the manufacturing process is simple, but peeling occurs between the lead frame and resin due to thermal stress

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidadhesion strength
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The invention applies a rough surface treatment (concave portions) locally at the chip connecting portion of the lead frame where thermal stress concentrates, while maintaining smooth surfaces in other areas. This localized modification increases adhesion strength precisely where needed without complicating the overall manufacturing process.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The rough surface treatment is performed in advance during lead frame fabrication, creating concave portions that will later enhance adhesion when resin is applied. This preliminary action prevents peeling before thermal stress occurs during module operation.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If the linear expansion coefficients of lead frame and resin are matched, then thermal stress is reduced, but peeling still occurs at the chip connecting portion

Engineering Contradiction:
Improveexpansion coefficient matchingVSAvoidpeeling resistance
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

Even with matched expansion coefficients, the invention introduces local surface roughness at the chip connecting portion. This creates mechanical interlocking that supplements the thermal compatibility achieved through expansion coefficient matching, providing dual protection against peeling.

Inventive Principle:
Principle #3Local quality

3Reliability

If solder wet-spreading is allowed, then electrical connection is ensured, but solder spreads excessively causing defects

Engineering Contradiction:
Improveelectrical connectionVSAvoidsolder spread control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention creates localized concave portions at specific regions of the lead frame. These concave portions act as solder barriers that control wet-spreading, allowing solder to fill concave areas for electrical connection while preventing excessive spread into unwanted regions.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the adhesion strength between the lead frame and resin, reducing peeling and resin cracking, thereby improving the durability and reliability of the semiconductor module.

Implementation Method 1

formed by laser irradiation or particle injection

Methodology Applied
Scientific EffectLaser irradiation: Laser

Implementation Method 2

formed by laser irradiation or particle injection

Methodology Applied
Scientific EffectParticle injection:

Implementation Method 3

inhibit solder wet-spreading

Methodology Applied
Scientific EffectWetting: Wetting

Data Source

PatentUS20220278039A1Semiconductor module and method for manufacturing semiconductor module
Publication Date: 2022.09.01 FUJI ELECTRIC CO LTD
  • US20220278039A1 patent drawing
  • US20220278039A1 patent drawing
  • US20220278039A1 patent drawing

AI summary

Provided is a semiconductor module including: an insulating circuit board having a circuit pattern formed in one surface; a semiconductor chip placed in the insulating circuit board; and a wiring portion for electrically connecting the semiconductor chip and the circuit pattern. The wiring portion includes a chip connecting portion connected to the semiconductor chip. A surface of the chip connecting portion includes: a plurality of concave portions; and a flat portion disposed between two concave portions.