Semiconductor Module Layout for Low Parasitic Inductance
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Solution Overview
Problem
Conventional semiconductor modules with bridge circuits experience insufficient reduction of parasitic inductance due to simple modularization of current paths, particularly when using wide band gap semiconductor chips at high frequencies.
Innovation Solution
A semiconductor module configuration where the first and third semiconductor chips are disposed on a high side, and the second and fourth chips on a low side, with symmetric wiring patterns and intermediate point terminals, allowing equal current path lengths and opposite current directions to cancel magnetic fields, thereby reducing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple modularization of current paths is performed, then device complexity is reduced, but parasitic inductance cannot be sufficiently reduced
Solution Approach 1:
The patent applies asymmetry by arranging intermediate point terminals and wiring patterns in specific asymmetric positions relative to semiconductor chips. The first intermediate point terminal is positioned closer to the first semiconductor chip than to the third semiconductor chip, creating unequal current path segments that compensate for the symmetric chip arrangement, thereby reducing overall parasitic inductance while maintaining modular simplicity
Solution Approach 2:
The patent introduces a new spatial dimension by positioning the first power source terminal above the fifth wiring pattern in a non-contact state. This vertical arrangement creates a three-dimensional current path that reduces parasitic inductance without increasing planar complexity, allowing the module to achieve low inductance through spatial optimization rather than complex two-dimensional routing
2Productivity
If wide band gap semiconductor chips are used for high frequency operation, then productivity and power efficiency are improved, but parasitic inductance causes increased power loss and ringing
Solution Approach 1:
The patent applies local quality by optimizing specific regions of the circuit board with different wiring patterns and terminal positions. The fifth wiring pattern is designed with specific trace widths and routing paths in different areas to minimize inductance locally, while the intermediate point terminals are positioned to create optimal current distribution in high-stress regions, enabling high-frequency operation with reduced power loss
Solution Approach 2:
The patent changes geometric parameters of the wiring patterns and terminal positions to reduce parasitic inductance. By adjusting the distances between terminals and chips, the routing paths of wiring patterns, and the spatial relationships in three-dimensional space, the patent optimizes the electrical characteristics to support high-frequency wide band gap semiconductor operation with minimal power loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic inductance by equalizing current path lengths and canceling magnetic fields, improving efficiency and performance at high frequencies.
Implementation Method 1
allowing equal current path lengths and opposite current directions to cancel magnetic fields, thereby reducing parasitic inductance
Data Source
AI summary
In a semiconductor module, first and third chips are disposed symmetrically with respect to a center line. Second and fourth chips are disposed symmetrically with respect to the center line. First and third wiring patterns are disposed symmetrically with respect to the center line. Second and fourth wiring patterns are disposed symmetrically with respect to the center line. Two intermediate points are disposed symmetrically with respect to the center line. Two second power terminals are disposed symmetrically with respect to the center line. A fifth wiring pattern and a first power terminal are disposed symmetrically with respect to the center line. The intermediate points are adjacent to each other on one side of the module. All power terminals are on the other side of the module. The first power terminal is above the fifth wiring pattern in a non-contact state and connects the first and third wiring patterns.