Semiconductor Module Layout for Low-Inductance Thermal Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor module arrangements face challenges in achieving a compact size with high thermal properties, high current carrying capability, and low inductance while maintaining cost-effectiveness due to large distances between semiconductor elements and high material costs.
Innovation Solution
A semiconductor module arrangement with a substrate, metal layer, and semiconductor components where each component has electrodes facing towards and away from the substrate, electrically coupled by metallic layers, allowing for reduced spacing and efficient heat dissipation, and a metal layer coupling electrodes to each other, reducing inductance and material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If large distances are maintained between semiconductor elements to meet thermal requirements, then thermal properties are improved, but the module size increases and current carrying capability decreases
Solution Approach 1:
The patent transitions from planar arrangement of semiconductor elements on a substrate to a three-dimensional stacked configuration. Multiple semiconductor components are arranged vertically between the substrate and metal layer, utilizing the third dimension (height) to increase density while maintaining thermal performance through controlled spacing in the vertical direction.
Solution Approach 2:
The metal layer serves multiple functions simultaneously: it acts as an electrical connection element coupling electrodes, a thermal management component for heat dissipation, and a structural element defining the module's upper boundary. This multi-functionality reduces the need for separate components, thereby reducing overall module size.
2Reliability
If conventional substrate arrangements with metallization layers are used, then electrical connections are established, but inductance is high and current carrying capability is limited
Solution Approach 1:
The electrical connection path is segmented into multiple parallel conductive paths through the metal layer and electrode arrangements. By distributing current flow across multiple parallel connections between semiconductor components and the metal layer, the overall inductance is reduced while maintaining reliable electrical connections.
Solution Approach 2:
The patent moves from two-dimensional metallization patterns on substrate surfaces to three-dimensional electrode and metal layer configurations. The vertical stacking of electrodes and metal layers creates shorter current paths and enables parallel conduction channels, thereby reducing inductance while improving current carrying capability.
3Reliability
If multiple bonding connections and metallization layers are used to ensure electrical and thermal performance, then reliability is improved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent combines multiple functions into integrated structures: the metal layer integrates electrical connection, thermal management, and structural support functions. The electrode arrangements merge electrical connectivity with mechanical positioning, reducing the number of separate bonding connections needed while maintaining reliability.
Solution Approach 2:
The semiconductor components are pre-configured with electrodes and metallic layers during manufacturing, establishing electrical and thermal pathways before final assembly. This preliminary structuring simplifies the assembly process and reduces the complexity of on-site bonding operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a smaller, more robust semiconductor module with improved thermal stability, reduced inductance, and lower costs by allowing separate testing of components and minimizing bonding connections.
Implementation Method 1
A first metallic layer is attached to the first electrode of the semiconductor chip by means of an electrically conducting connection layer, and a second metallic layer is attached to the second electrode of the semiconductor chip by means of an electrically conducting connection layer
Implementation Method 2
a dielectrically insulating layer covering surfaces of the semiconductor chip
Implementation Method 3
the metal layer is coupled to the respective electrodes facing away from the substrate of the plurality of semiconductor components, thereby electrically coupling the respective electrodes to each other
Data Source
Figure 1~2
Figure 3~4
AI summary
A semiconductor module arrangement comprises a substrate, a metal layer, and a plurality of semiconductor components arranged on the substrate, and between the metal layer and the substrate. Each semiconductor component of the plurality of semiconductor components comprises a semiconductor chip having a first electrode arranged on a first side of the semiconductor chip, and a second electrode arranged on a second side of the semiconductor chip opposite the first side, a first metallic layer attached to the first electrode of the semiconductor chip by means of an electrically conducting connection layer, a second metallic layer attached to the second electrode of the semiconductor chip by means of an electrically conducting connection layer, and a dielectrically insulating layer covering surfaces of the semiconductor chip, wherein surfaces of the first and second metallic layers that face away from the semiconductor chip are at least partially uncovered by the dielectrically insulating layer. Each semiconductor component of the plurality of semiconductor components is arranged on the substrate such that one of its first and second electrode faces towards and is electrically coupled to the substrate, and the respective other one of the first and second electrode faces away from the substrate, and the metal layer is coupled to the respective electrodes facing away from the substrate of the plurality of semiconductor components, thereby electrically coupling the respective electrodes to each other.