Semiconductor Module Metallization for Low Parasitic Inductance
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Solution Overview
Problem
Existing semiconductor power chip modules face challenges in forming interconnections between transistors, diodes, and passive components with low parasitic inductances and improved heat dissipation properties.
Innovation Solution
A semiconductor module comprising a carrier with semiconductor chips, an encapsulation layer, and a metallization layer that forms electrical connections between the chips, utilizing via connections and metallic areas to reduce parasitic inductances and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If components are mounted as individual components on a printed circuit board, then assembly is simplified, but space requirements increase and interconnection length increases leading to higher parasitic inductances
Solution Approach 1:
The patent combines multiple components (semiconductor chips, passive components, and interconnections) into a single integrated semiconductor module package. This merging eliminates the need for separate component mounting on a printed circuit board, thereby reducing overall space requirements while maintaining assembly simplicity through a unified fabrication process.
Solution Approach 2:
The patent transitions from a two-dimensional PCB layout to a three-dimensional integrated module structure. By stacking components vertically and using multi-layer metallization, the design achieves compact integration that reduces parasitic inductances through shorter interconnection paths while maintaining ease of manufacture through standardized packaging processes.
2Volume of moving object
If components are integrated into a single housing to form a multi-chip module, then space requirements are reduced, but forming interconnections with low parasitic inductances becomes more difficult
Solution Approach 1:
The patent segments the interconnection structure into multiple functional layers: substrate metallization, encapsulation layer with embedded vias, and top metallization. This segmentation allows each layer to be optimized independently for its specific function, achieving low parasitic inductances through precise control of each segment while maintaining overall integration benefits.
Solution Approach 2:
The patent introduces an encapsulation layer as an intermediary between the substrate and top metallization. This encapsulation layer contains embedded via connections that serve as intermediaries for electrical connections, allowing precise control of interconnection paths and reducing parasitic inductances while maintaining the compact integrated structure.
3Temperature
If traditional mounting methods are used, then heat dissipation is adequate, but space requirements increase and assembly complexity increases
Solution Approach 1:
The patent creates a multi-functional semiconductor module where a single integrated structure simultaneously provides electrical interconnections, mechanical support, and heat dissipation. The metallization layers and substrate serve multiple functions including electrical conduction and thermal management, reducing assembly complexity while maintaining effective heat dissipation.
Solution Approach 2:
The patent employs composite structures combining different materials with complementary properties: conductive metallization layers for electrical connections, encapsulation materials for mechanical support and insulation, and thermally conductive pathways for heat dissipation. This composite approach achieves effective heat management while simplifying the overall assembly process.
Data Source
AI summary
The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.