Semiconductor Module Heat Dissipation via Nested Metal Plates

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Solution Overview

Problem

The existing electronic devices with power transistors face challenges in improving heat dissipation properties while maintaining reliability and reducing size and weight, particularly in electric vehicles where both efficiency and compactness are crucial.

Innovation Solution

The solution involves a semiconductor module configuration where larger metal plates are joined to the double-side electrodes of the packages, which are then connected to cooling plates via insulating members, enhancing the heat dissipation area without increasing the module's size or weight.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If larger metal plates are joined to the double-side electrodes of the packages, then heat dissipation area is improved, but module size and weight increase

Engineering Contradiction:
Improveheat dissipation areaVSAvoidmodule weight
Core Design Contradiction:
TemperatureVSWeight of stationary object

Solution Approach 1:

The patent applies nesting by placing the metal plates within the bounding box of the semiconductor package footprint. The metal plates are positioned on the front and rear surfaces of the package, utilizing the vertical space and overlapping the package area, thereby increasing heat dissipation area without increasing the module's external dimensions or weight.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent transitions from two-dimensional heat dissipation (within the package plane) to three-dimensional heat dissipation by extending metal plates to the front and rear surfaces of the package. This adds a vertical dimension to the heat dissipation path, allowing heat to be dissipated from multiple surfaces simultaneously without increasing the module's planar footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If larger metal plates are joined to the double-side electrodes of the packages, then heat dissipation area is improved, but module size increases

Engineering Contradiction:
Improveheat dissipation areaVSAvoidmodule size
Core Design Contradiction:
TemperatureVSArea of stationary object

Solution Approach 1:

The metal plates are nested within the package footprint boundaries, positioned on the front and rear surfaces. This nesting approach allows the heat dissipation area to be increased by utilizing the vertical extent of the package rather than expanding the horizontal footprint, thus improving heat dissipation without increasing module size.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The solution moves heat dissipation from a two-dimensional planar expansion to a three-dimensional vertical extension. By attaching metal plates to the front and rear surfaces of the package, the heat dissipation area is increased in the vertical dimension while maintaining the same planar footprint, effectively resolving the size contradiction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If junction temperature is reduced by improving heat diffusion, then reliability is improved, but device complexity increases

Engineering Contradiction:
ImprovereliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the electrical connection function and the heat dissipation function into a single integrated structure. The metal plates are electrically connected to the double-side electrodes of the power transistors and simultaneously serve as heat dissipation paths. This merging reduces device complexity by eliminating the need for separate heat sinks and electrical connections, while effectively reducing junction temperature to improve reliability.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces the junction temperature of the power transistors by improving heat diffusion, thereby enhancing the heat dissipation property and maintaining the compact size and reduced weight of the semiconductor module.

Implementation Method 1

The second surface of the first metal plate of the first sealing body is electrically coupled to a first terminal via a first conductor layer. The eighth surface of the fourth metal plate of the second sealing body is electrically coupled to a second terminal via a second conductor layer. The fourth surface of the second metal plate of the first sealing body and the sixth surface of the third metal plate of the second sealing body are electrically coupled to an output terminal via a third conductor layer.

Methodology Applied
Scientific EffectHeat conduction: Conduction (thermal)

Implementation Method 2

the double-side electrodes of the packages, which are then connected to cooling plates via insulating members, enhancing the heat dissipation area

Methodology Applied
Scientific EffectThermal conduction through insulating material: Conduction (thermal)

Data Source

PatentUS10361174B2Electronic device
Publication Date: 2019.07.23 RENESAS ELECTRONICS CORP
  • US10361174B2 patent drawing
  • US10361174B2 patent drawing
  • US10361174B2 patent drawing

AI summary

An improvement is achieved in the heat dissipation property of an electronic device including power transistors. A semiconductor module includes first and second packages included in an inverter circuit. In the first package, a semiconductor chip having a high-side power transistor is embedded. In the second package, a semiconductor chip having a low-side power transistor is embedded. At the both wide surfaces of the first and second packages, first metal electrodes electrically coupled to respective collector electrodes of the power transistors and second metal electrodes electrically coupled to respective emitter electrodes of the power transistors are exposed. To the first and second metal electrodes of the first and second packages, four respective bus bar plates having areas larger than those of the first and second metal electrodes are joined.