Power Semiconductor Module Pad Layout for Bonding Reliability
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Solution Overview
Problem
Existing power semiconductor devices face issues with bonding defects, detachment, electrical short-circuits, and reliability due to reduced size and misalignment, leading to high defect rates and inefficient high-voltage testing, especially in inverters for eco-friendly vehicles.
Innovation Solution
A power semiconductor module design featuring a common gate and source pad configuration that expands the connection area between multiple devices, surrounded by a molding layer for insulation and improved thermal characteristics, allowing for high-voltage testing before assembly and reducing exposure to foreign substances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of power semiconductor devices and gate electrodes is reduced to maximize active area, then device integration density is improved, but bonding reliability deteriorates due to insufficient bonding strength and misalignment
Solution Approach 1:
The invention introduces a multi-layer pad structure consisting of a first pad, a second pad, and a third pad. The first pad is formed on the substrate, the second pad is formed on the power semiconductor device, and the third pad connects them. This segmentation allows each pad to be optimized independently - the first and third pads can be larger to ensure reliable bonding, while the second pad on the device can be smaller to maximize active area.
Solution Approach 2:
The third pad acts as an intermediary element between the first pad (on substrate) and the second pad (on device). It provides a transition zone that compensates for misalignment and ensures reliable electrical connection. The intermediary pad structure allows bonding to occur at multiple locations, distributing the bonding stress and improving overall bonding reliability even when device size is reduced.
2Device complexity
If conventional bonding methods are used with reduced-size devices, then manufacturing process simplicity is maintained, but defect rate increases due to gate open and gate-source short
Solution Approach 1:
The bonding process is segmented into multiple stages corresponding to the multi-layer pad structure. First, the power semiconductor device is bonded to the second pad; then the first pad is bonded to the substrate; finally, the third pad establishes the electrical connection. This segmentation allows each bonding step to be optimized and controlled separately, reducing the overall defect rate while maintaining process simplicity.
Solution Approach 2:
The pad structures are pre-formed on both the substrate and the power semiconductor device before the bonding process. This preliminary action ensures that the bonding surfaces are already prepared with appropriate geometry and material properties, reducing the risk of bonding defects and eliminating the need for complex real-time adjustment during bonding.
3Manufacturing precision
If power semiconductor devices are mounted with spacing compensation using spacers, then alignment tolerance is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The invention merges the alignment compensation function into the pad structure itself. The multi-layer pad configuration inherently provides alignment tolerance because the bonding can occur at multiple locations across the pad surfaces. This eliminates the need for separate spacer components and their associated manufacturing steps, reducing overall device complexity while maintaining manufacturing precision.
4Productivity
If high-voltage testing is performed on incompletely tested devices, then production efficiency is maintained, but reliability is compromised due to insulation problems and sparks
Solution Approach 1:
The multi-layer pad structure and surrounding insulation layers are formed in advance during the manufacturing process, creating a complete and isolated testing structure before high-voltage testing occurs. This preliminary preparation ensures that all insulation paths are established and can be properly tested, allowing for safe and effective high-voltage testing without the risk of sparks or insulation breakdown.
Data Source
AI summary
A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.