Power Semiconductor Module Parasitic Inductance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power semiconductor modules experience voltage oscillations due to parasitic inductance and junction capacity differences, leading to electromagnetic failures and reduced manufacturing yield, especially in high-voltage applications where switching times are longer and energy storage is higher.
Innovation Solution
The power semiconductor module electrically connects main electrodes of semiconductor switching elements via a conductor member, such as a wire, to reduce resonant voltage occurrences caused by parasitic inductance and junction capacity, thereby minimizing voltage oscillations during switching-off times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor elements are connected in parallel to increase current handling capability, then the power handling capacity is improved, but the wiring distance to each element becomes different causing parasitic inductance differences and switching timing shifts
Solution Approach 1:
The patent applies equipotentiality by connecting all semiconductor elements to a common potential reference point through the conductor member. This ensures that despite different physical positions and wiring distances, all elements experience the same electrical potential conditions during switching, eliminating timing shifts caused by parasitic inductance differences.
Solution Approach 2:
The patent merges the connection paths of multiple semiconductor elements by introducing a common conductor member that consolidates their individual connections. This merging of connection paths equalizes the electrical characteristics and reduces the impact of varying wiring distances on switching timing.
2Quantity of substance
If the number of semiconductor elements is increased to handle larger currents, then the current capacity is improved, but voltage oscillation and electromagnetic interference increase due to parasitic inductance and junction capacity
Solution Approach 1:
The conductor member acts as an intermediary element that mediates the electrical interaction between multiple semiconductor elements. By providing a common connection path, it reduces the direct coupling between elements that would otherwise create strong electromagnetic interference and voltage oscillations through parasitic inductance and capacitance interactions.
3Strength
If high-voltage semiconductor elements with thicker semiconductor regions are used to increase withstand voltage, then the voltage blocking capability is improved, but the switching time becomes longer due to extended charge ejection time from widened depletion layers
Solution Approach 1:
The patent applies preliminary anti-action by pre-connecting semiconductor elements through the common conductor member before switching operations occur. This pre-established connection path reduces the effective parasitic inductance and facilitates faster charge ejection from the widened depletion layers, counteracting the natural tendency toward longer switching times in high-voltage devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses voltage oscillations, preventing electromagnetic failures and improving manufacturing yield by equalizing charge storage across semiconductor elements and reducing parasitic inductance, thus enhancing the reliability of power conversion systems.
Implementation Method 1
the wiring distance from an external electrode to each semiconductor element becomes different. This situation causes a difference to occur in the parasitic inductance
Implementation Method 2
a difference to occur in the parasitic inductance. Moreover, this difference in the parasitic inductance and a variation in the characteristics of each semiconductor element cause a shift to occur in the timing of the switching
Implementation Method 3
the LC resonance is caused to occur by the parasitic capacity C of each semiconductor element and the parasitic inductance L of the wirings which connect the respective semiconductor elements to each other. This LC resonance results in the occurrence of the large voltage oscillation
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The respective main electrodes (52, 52') of the semiconductor switching elements (50, 50') such as IGBTs, which are respectively mounted on the plurality of insulating boards (20, 20'), are electrically connected to each other via the conductor member (45). This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element (50, 50').