Semiconductor Module PCB Inlay Structure for Reliable Chip Bonding
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Solution Overview
Problem
Existing semiconductor modules face challenges in miniaturization and reliability due to the need for bonding areas in wiring structures, which complicates component alignment and inspection, especially in designs using wires or printed circuit boards with pin terminals.
Innovation Solution
A semiconductor module design featuring a multi-layer printed circuit board with metal inlays embedded between semiconductor chips and an insulating substrate, allowing for high-density mounting and miniaturization while improving component alignment and inspection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-layer wiring structure with pin terminals is used, then electrical connection is achieved, but manufacturing complexity and inspection difficulty increase
Solution Approach 1:
The patent transitions from planar wiring structures to three-dimensional stacked configurations. Multiple wiring layers are arranged vertically with metal inlays extending through the stack, enabling electrical connections in the thickness direction. This dimensional change reduces the number of required pin terminals and simplifies the overall wiring structure while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent combines multiple functions into integrated structures. Metal inlays serve dual purposes as both structural support elements and electrical connection pathways. The wiring layers are merged with the metal inlay structure to form a unified three-dimensional interconnection system, reducing the need for separate pin terminals and simplifying manufacturing.
2Reliability
If bonding areas are provided in wiring structures, then electrical connection is established, but component alignment becomes more difficult
Solution Approach 1:
The patent incorporates metal inlays and wiring structures into the substrate before mounting semiconductor chips. This preliminary preparation of electrical connection structures eliminates the need for post-mounting alignment and bonding operations, thereby improving component alignment precision while ensuring reliable electrical connections are already in place.
3Reliability
If conventional wiring structures with pin terminals are used, then electrical connection is achieved, but inspection reliability decreases
Solution Approach 1:
The patent utilizes three-dimensional stacked wiring layers and metal inlays that are visible from the upper surface of the substrate. This dimensional arrangement allows inspection systems to detect and measure electrical connection structures without requiring disassembly or specialized access, thereby improving inspection reliability while maintaining electrical connection integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves module miniaturization and enhances inspection reliability by providing bonding areas at the uppermost level of the printed circuit board, reducing issues associated with wiring structures using wires or printed circuit boards with pin terminals.
Implementation Method 1
a lowermost wiring layer provided at a lowermost level of the wiring substrate and bonded to a top surface of the insulating substrate
Implementation Method 2
a metal inlay embedded in the wiring substrate between the semiconductor chip and the insulting substrate, the metal inlay being electrically connected to the semiconductor chip
Data Source
AI summary
A semiconductor module, including: an insulating substrate; a semiconductor chip; and a wiring substrate. The wiring substrate includes: an insulating layer; a plurality of wiring layers formed in the insulating layer, the plurality of wiring layers including a lowermost wiring layer provided at a lowermost level of the wiring substrate and bonded to a top surface of the insulating substrate, and an uppermost wiring layer provided at an uppermost level of the wiring substrate, the uppermost wiring layer being a semiconductor chip mounting wiring layer to which the semiconductor chip is bonded; and a metal inlay embedded in the wiring substrate between the semiconductor chip and the insulting substrate, the metal inlay being electrically connected to the semiconductor chip.