Power Semiconductor Module with Preform Alloy for Short Circuit Failure Mode
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Solution Overview
Problem
Existing power semiconductor modules face issues with short circuit failure mode (SCFM) capabilities, including aging of dry electrical contacts, resistance in current paths, mechanical complexity, limited current load, and high costs, particularly in press-pack modules like StakPak, which are complex and costly.
Innovation Solution
A power semiconductor module design featuring electrically and thermally conductive baseplates with preforms that form a conductive alloy upon failure, eliminating dry contacts and mechanical complexity through bonding layers, reducing package volume and manufacturing costs, and enhancing heat dissipation and SCFM capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If press-pack modules with spring-loaded components are used to achieve SCFM capability, then short circuit failure mode capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the spring-loaded mechanical components from the press-pack module design. Instead of using springs to apply pressure and create dry contacts, the invention uses a simplified stack structure where ceramic insulators directly support the electrical contacts, eliminating the need for mechanical pressure application mechanisms while maintaining SCFM capability through the conductive path formed by melted materials during failure events
Solution Approach 2:
The module is divided into discrete functional layers: ceramic insulator segments, metal contact segments, and semiconductor chip segments. Each layer performs a specific function and can be independently manufactured and assembled, simplifying the overall structure while enabling the desired failure mode behavior through the interaction of these segmented components
2Reliability
If spring-loaded components are used to maintain contact pressure, then dry contact quality is improved, but current load capability is limited
Solution Approach 1:
The patent relies on phase transition to liquid state during failure events to maintain conductive paths without mechanical pressure. The liquid metal formed during melting can carry higher currents than solid contact interfaces, thereby increasing current load capability while eliminating the need for spring-loaded pressure application mechanisms that limited power handling
3Reliability
If aluminum and silver materials are used to form eutectic alloy for SCFM, then melting temperature is reduced for reliable short circuit path formation, but material cost increases
Solution Approach 1:
The patent changes the material composition parameters to use aluminum and silver in specific configurations that form eutectic alloys with lower melting points. This parameter change enables reliable short circuit path formation at lower temperatures while the patent optimizes the quantity and distribution of these materials to control costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved reliability, reduced resistance in current paths, lower manufacturing costs, and enhanced heat dissipation, allowing for prolonged operation and efficient maintenance in case of short circuit failures, with a compact design suitable for various high-power applications.
Implementation Method 1
the material of the power semiconductor chip and the material of the platelet are heated such that an eutectic metallic alloy is formed which provides a short circuit path over the power semiconductor chip
Implementation Method 2
an eutectic metallic alloy is formed which provides a short circuit path
Implementation Method 3
the bottom electrode of the power semiconductor chip is thermally and electrically connected to the bottom electrode-baseplate via a first bonding layer
Implementation Method 4
the top electrode of the power semiconductor chip is thermally and electrically connected to a first side of the first preform via a second bonding layer
Implementation Method 5
a power semiconductor module design featuring electrically and thermally conductive baseplates with preforms that form a conductive alloy upon failure, eliminating dry contacts and mechanical complexity through bonding layers, reducing package volume and manufacturing costs, and enhancing heat dissipation
Data Source
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AI summary
A semiconductor device (509a, b) comprises a semiconductor chip (504a, b) comprising a bottom electrode and a top electrode and a bottom electrode- baseplate (502). The bottom electrode-baseplate (502) is electrically and thermally conductive. The semiconductor device (509a, b) comprises a top electrode- baseplate (508). The top electrode-baseplate (508) is electrically and thermally conductive. The semiconductor device (509a, b) comprises a first preform (506a, b) made of material configured for supporting a creation of an electrically conductive alloy when being melted. In order to provide a semiconductor device having enhanced characteristics, the bottom electrode of the semiconductor chip (504a, b) is thermally and electrically connected to the bottom electrode-baseplate (502) via a first bonding layer (618), the top electrode of the semiconductor chip (504a, b) is thermally and electrically connected to a first side of the first preform (506a, b) via a second bonding layer (620), and the second side of the first preform (506a, b) is thermally and electrically connected to the top electrode- baseplate (508) via a third bonding layer (624).