Semiconductor Module 3D Stacking for Data Density
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Solution Overview
Problem
Current semiconductor modules for optical communication face challenges in maximizing data transmission per volume and energy efficiency between photonics chips and driver chips, with limited design freedom for high integration and miniaturization due to larger photonics chip sizes and insufficient laminating strength.
Innovation Solution
The semiconductor module design involves a photonics chip and a driver chip with matching planar sizes, where the photonics chip's surface is bonded to the driver chip's surface, with direct contact between their wirings to enhance data transmission efficiency and laminating strength, allowing for increased integration and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the photonics chip size is made larger to reduce propagation loss and power consumption, then energy efficiency is improved, but the volume density of data transmission and module miniaturization are worsened
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional stacking, where the driver chip is mounted on the back surface of the photonics chip. This vertical integration allows both chips to coexist in a compact volume while maintaining short electrical connection paths, thereby reducing power consumption without increasing the module's footprint.
Solution Approach 2:
The driver chip is positioned on the back surface of the photonics chip, effectively nesting one chip within the spatial envelope of the other. This nested configuration maximizes space utilization and achieves miniaturization while keeping the electrical connection distance short to minimize power loss.
2Ease of manufacture
If conventional mounting methods are used, then ease of manufacture is maintained, but laminating strength between chips is insufficient
Solution Approach 1:
The patent combines the electrical connection function and mechanical bonding function into a single integrated process. By forming conductive bumps that serve both as electrical contacts and as bonding elements during co-firing, the design achieves strong lamination while maintaining manufacturing simplicity through a unified process step.
Solution Approach 2:
The bonding interface uses a composite structure involving conductive bumps (metal) embedded in a ceramic substrate, creating a multi-material joint that provides both electrical conductivity and mechanical strength. The co-firing process creates a metallurgical bond between the copper bumps and the ceramic, achieving superior bonding strength.
3Manufacturing precision
If design freedom is limited, then manufacturing precision is maintained, but high integration and miniaturization are worsened
Solution Approach 1:
The conductive bumps are pre-formed on the driver chip before mounting, and their positions are precisely determined in advance. The co-firing process then automatically aligns these pre-positioned bumps with corresponding pads on the photonics chip, eliminating the need for complex real-time alignment procedures and enabling high integration with maintained precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design maximizes data transmission per unit volume, improves energy efficiency, and enables miniaturization of the semiconductor module by ensuring direct contact and reduced resistivity between the chips, thereby enhancing overall performance.
Implementation Method 1
the surface of the first semiconductor chip is bonded to the surface of the second semiconductor chip
Data Source
AI summary
The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements. A top surface of the first semiconductor chip is laminated with a top surface of the second semiconductor chip such that the first and second wirings are directly contacted with each other.