Semiconductor Module Surge Voltage Absorption
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Solution Overview
Problem
Existing semiconductor modules fail to reliably reduce surge voltage between the positive-side and negative-side input terminals of power conversion circuits due to elongated distances between transistors and snubber capacitors, leading to insufficient voltage absorption.
Innovation Solution
A semiconductor module configuration with vertically mounted transistors and a surge voltage absorbing device, where the transistors are connected in series and the surge voltage absorbing device is placed between them to reduce inductance and enhance voltage absorption, with a conductive plate coupling the transistors and snubber devices to shorten current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the snubber capacitor is placed separately from the transistors to prevent heat degradation, then the transistors are thermally protected, but the distance between transistors and snubber capacitor increases causing insufficient surge voltage absorption
Solution Approach 1:
The patent merges the snubber capacitor with the transistor assembly by placing it on the same insulating substrate and electrically connecting it through conductive patterns. This integration allows the snubber capacitor to be positioned close to the transistor for effective surge voltage absorption while the insulating substrate provides thermal isolation to protect the transistor from heat degradation.
2Reliability
If the distance between transistors and surge voltage absorbing devices is reduced to improve voltage absorption, then surge voltage is effectively reduced, but the thermal management becomes more difficult
Solution Approach 1:
The insulating substrate acts as an intermediary between the transistor and the snubber capacitor. It provides electrical connection paths through conductive patterns while simultaneously providing thermal isolation. This mediator allows the components to be positioned close together for effective surge voltage absorption while preventing heat transfer from the transistor to the snubber capacitor.
3Ease of manufacture
If the current path is lengthened to connect transistors and surge voltage absorbing devices, then the circuit layout is simplified, but the inductance increases reducing voltage absorption effectiveness
Solution Approach 1:
The patent utilizes the two-dimensional plane of the insulating substrate to create optimized current paths. By arranging conductive patterns in specific geometric configurations on the substrate surface, the design achieves short current paths with low inductance while maintaining layout simplicity. The conductive patterns are routed to minimize path length between transistors and snubber capacitors without requiring complex three-dimensional interconnections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces surge voltage by minimizing inductance and ensuring closer proximity of transistors to the surge voltage absorbing devices, thereby stabilizing the voltage in power conversion circuits.
Implementation Method 1
a surge voltage absorbing device connecting the first input interconnect pattern and the second input interconnect pattern, and configured to absorb surge voltage
Implementation Method 2
a plate member disposed on the first vertical transistor and the second vertical transistor, and having a back-side conductive area, wherein the second main electrode pad and the third main electrode pad are electrically coupled to each other through the back-side conductive area of the plate member
Data Source
AI summary
A semiconductor module according to an embodiment includes a circuit substrate, a first vertical transistor having a first main electrode pad facing and coupled to a first input interconnect pattern of the circuit substrate, and having a first gate electrode pad coupled to a first control interconnect pattern of the circuit substrate, a second vertical transistor having a fourth main electrode pad facing and coupled to a second input interconnect pattern of the circuit substrate, and having a second gate electrode pad facing and coupled to a second control interconnect pattern of the circuit substrate, a surge voltage absorbing device connecting the first and second input interconnect patterns to absorb surge voltage, and a plate member connecting a second main electrode pad of the first vertical transistor and a third main electrode pad of the second vertical transistor.