Power Semiconductor Module Terminal Overlap for Inductance Reduction
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Solution Overview
Problem
Conventional power semiconductor modules for three-level inverters face challenges in reducing mutual inductance and electromagnetic noise, while also requiring complex wiring configurations that increase manufacturing costs and make it difficult to attach external connections.
Innovation Solution
A power semiconductor module design that aligns the P-terminal, M-terminal, and N-terminal connectors farther away from the control terminals, with the output terminal and M-terminal overlapping to reduce mutual inductance, and arranges the P-terminal, M-terminal, and N-terminal outside the case to minimize electromagnetic noise and simplify external connection attachment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the terminals are arranged in a conventional configuration, then the module structure is simple, but the mutual inductance is large and electromagnetic noise is increased
Solution Approach 1:
The patent applies dimensional arrangement by positioning terminals at different spatial locations and orientations within the module. The P-terminal, N-terminal, and M-terminal are arranged in specific three-dimensional configurations that increase separation distance and reduce mutual inductance, directly addressing the electromagnetic noise issue while managing structural complexity.
Solution Approach 2:
The terminal arrangement employs asymmetric positioning where terminals are not uniformly distributed but placed at specific asymmetric locations optimized for reducing electromagnetic interference. This asymmetric layout allows for minimized mutual inductance between power terminals while maintaining manufacturing feasibility.
2Object-affected harmful factors
If complex wiring configurations are used to reduce mutual inductance, then electromagnetic noise is reduced, but manufacturing cost increases and external connection attachment becomes difficult
Solution Approach 1:
The patent implements local quality optimization by arranging terminals with specific local characteristics - certain terminals are positioned closer to each other while others are separated, depending on their electrical function and current requirements. This localized arrangement reduces mutual inductance where critical while maintaining ease of connection where applicable.
Solution Approach 2:
The terminal arrangement follows a standardized pattern or template that can be replicated across multiple modules. This copying approach allows for reduced mutual inductance through optimized geometry while maintaining consistent, simplified manufacturing processes and external connection procedures across production batches.
Data Source
AI summary
In a semiconductor module according to certain aspects the invention, a U-terminal and an M-terminal overlap each other in a manner to reduce inductance and to further to reduce the size of snubber capacitor. In certain aspects of the invention, a P-terminal, M-terminal, N-terminal, and U-terminal are arranged such that the U-terminal, through which currents flow in and out, is arranged farthest away from control electrodes to reduce the noises superposed to control electrodes, and the P-terminal, M-terminal, N-terminal, and U-terminal are aligned to facilitate attaching external connection bars thereto. A power semiconductor module according to aspects of the invention can facilitate reducing the wiring inductance inside and outside the module, reducing the electromagnetic noises introduced into the control terminals, and attaching the external wirings to the terminals thereof simply and easily.