Semiconductor Module Packaging for Compact Thermal Management
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Solution Overview
Problem
Power semiconductor module arrangements face challenges with large size due to thermal requirements, high costs, and difficulty in testing individual semiconductor elements, which are often not separately packaged.
Innovation Solution
The semiconductor module arrangement includes pre-packaged semiconductor components with metallic layers attached to electrodes, covered by a dielectric insulating layer, allowing for separate testing and improved thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor elements are mounted directly on substrate metallization layers, then electrical connections are established, but thermal requirements force large distances between elements increasing module size
Solution Approach 1:
The patent transitions from planar mounting on substrate metallization layers to three-dimensional mounting on dedicated carrier substrates with raised mounting surfaces. This vertical dimensionality change allows heat to be conducted through the thickness of the carrier substrate to cooling plates, while electrical connections are established through conductive vias, thereby decoupling thermal management from lateral spacing requirements.
Solution Approach 2:
The patent introduces carrier substrates as intermediary components between the semiconductor elements and the final cooling structure. These carrier substrates serve as dedicated thermal pathways with integrated cooling plates, acting as mediators that conduct heat away from the semiconductor elements without requiring large lateral distances between them on the main substrate.
2Temperature
If large distances are maintained between semiconductor elements for thermal management, then heat dissipation is improved, but the overall module size increases
Solution Approach 1:
The patent moves thermal management from the lateral plane to the vertical dimension by implementing cooling plates attached to the rear surfaces of carrier substrates. This allows heat to be dissipated through the thickness of the carrier substrates vertically, enabling compact lateral spacing of semiconductor elements while maintaining effective heat dissipation.
Solution Approach 2:
The patent segments the module into multiple carrier substrates, each carrying one or more semiconductor elements and equipped with its own cooling plate. This segmentation allows independent thermal management of each carrier substrate, enabling compact arrangement of multiple carriers on the main substrate without requiring large thermal spacing between individual semiconductor elements.
3Device complexity
If individual semiconductor elements are not separately packaged, then device complexity is reduced, but testing of individual elements becomes difficult or impossible
Solution Approach 1:
The patent segments the module into modular carrier substrates, where each carrier substrate can be independently tested before final assembly. The carrier substrates with mounted semiconductor elements and integrated cooling plates function as independent testable units, allowing individual element testing through the carrier substrate's electrical connections while maintaining relatively simple packaging.
Solution Approach 2:
The carrier substrates act as intermediary test platforms that provide accessible electrical connections and thermal management for the mounted semiconductor elements. These intermediaries enable testing of individual semiconductor elements through the carrier substrate's contact pads and vias without requiring complex direct access to each element's internal connections.
4Ease of manufacture
If conventional substrate mounting is used, then manufacturing is simplified, but environmental stability and thermal properties are insufficient
Solution Approach 1:
The patent employs composite carrier substrates that combine electrically conductive materials with thermally conductive properties. These composite substrates integrate multiple material properties (electrical conductivity, thermal conductivity, mechanical strength, and environmental stability) into a single manufactured component, maintaining ease of manufacture through standardized composite material fabrication processes while achieving superior environmental stability and thermal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces overall size, enhances thermal properties, increases environmental stability, and enables easy testing of individual components, resulting in higher yield and reduced costs.
Implementation Method 1
a first metallic layer (202) attached to the first electrode (201) of the semiconductor chip (20) by means of an electrically conducting connection layer (208), a second metallic layer (204) attached to the second electrode (203) of the semiconductor chip (20) by means of an electrically conducting connection layer (208)
Implementation Method 2
a dielectrically insulating layer (210) covering surfaces of the semiconductor chip (20), wherein surfaces of the first and second metallic layers (202, 204) that face away from the semiconductor chip (20) are not covered by the dielectrically insulating layer (210)
Data Source
AI summary
A semiconductor module arrangement includes a substrate and at least one semiconductor component arranged on the substrate. Each of the at least one semiconductor component includes a semiconductor chip having first and second electrodes, a first metallic layer attached to the first electrode of the semiconductor chip via an electrically conducting connection layer, a second metallic layer attached to the second electrode of the semiconductor chip via an electrically conducting connection layer, and a dielectrically insulating layer covering surfaces of the semiconductor chip. Surfaces of the first and second metallic layers that face away from the semiconductor chip are not covered by the dielectrically insulating layer.