Semiconductor Module PCB Layout With Upward External Terminals

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Solution Overview

Problem

Conventional power semiconductor modules with semiconductor chips on a conductive substrate connected to a printed wiring board via lead frames or bonding wires face an increase in size due to external terminal connections.

Innovation Solution

A semiconductor device configuration where semiconductor chips are mounted on a conductive substrate with a printed wiring board electrically connected, featuring a conductive substrate, semiconductor chips, a printed wiring board with insulating and conductive layers, and external terminals that extend upward to reduce size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor chips are connected to printed wiring board via lead frames or bonding wires, then electrical connection is achieved, but device size increases

Engineering Contradiction:
Improveelectrical connectionVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent removes the traditional lead frame structure from the semiconductor device. Instead of using lead frames to connect semiconductor chips to the printed wiring board, the invention directly integrates the chips with the board through simplified bonding wire connections, extracting the unnecessary intermediate component that was increasing device size.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a planar connection layout to a three-dimensional stacked architecture. Semiconductor chips are mounted vertically on the printed wiring board, with multiple layers and levels of connection, allowing electrical connections to be achieved in the vertical dimension rather than requiring extensive lateral space for lead frames.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If lead frames are used for external terminal connections, then electrical connectivity is ensured, but wiring area increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidwiring area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent eliminates the lead frame component entirely, removing the extensive wiring structure that occupied significant area on the circuit board. The electrical connectivity function is achieved through direct chip-to-board bonding wires, which require minimal wiring area compared to traditional lead frames.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses thin bonding wires instead of bulky lead frames to establish electrical connections. These fine wire bonds create compact connection paths that minimize the wiring area required while maintaining reliable electrical connectivity between components.

Inventive Principle:
Principle #30Flexible shells and thin films

3Ease of manufacture

If conventional connection structures are used, then manufacturing is achieved, but manufacturing complexity increases

Engineering Contradiction:
ImprovemanufacturingVSAvoidmanufacturing complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent removes the lead frame assembly step from the manufacturing process. Without lead frames, the manufacturing sequence is simplified to directly mounting semiconductor chips onto the printed wiring board and forming bonding wire connections, eliminating the complex steps of lead frame fabrication, attachment, and wiring.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent separates the connection function into distinct stages: chip mounting followed by bonding wire formation. This segmentation allows each manufacturing step to be optimized independently, with chips pre-prepared and bonded directly to the board in a streamlined process rather than being integrated into lead frame assemblies.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250157892A1Semiconductor device
Publication Date: 2025.05.15 FUJI ELECTRIC CO LTD
  • US20250157892A1 patent drawing
  • US20250157892A1 patent drawing
  • US20250157892A1 patent drawing

AI summary

A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips provided on the conductive substrate; a printed wiring board including a first conductive layer provided on the conductive substrate, an insulating layer provided on the first conductive layer, and a second conductive layer provided on the insulating layer and electrically connected to respective first electrodes of the semiconductor chips; and a first external terminal provided on the second conductive layer to extend upward from the second conductive layer.