Semiconductor Module Vertical Transistor Wiring for Low Inductance

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Solution Overview

Problem

In semiconductor modules used for power converters like inverters, the series connection of vertical transistor chips is hindered by potential fluctuations due to the inductance component of conducting wires, limiting the operational frequency.

Innovation Solution

A semiconductor module design where the first and second transistor chips are mounted on a substrate with specific wiring patterns, allowing direct electrical connections without the need for conducting wires between the drain and source electrode pads, thereby minimizing inductance-related fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conducting wires are used to connect the drain electrode pad of the lower arm transistor and the source electrode pad of the upper arm transistor in series, then the transistor chips can be connected together, but potential fluctuation occurs due to the inductance component of the conducting wire, limiting the operational frequency

Engineering Contradiction:
Improveconnection stabilityVSAvoidoperational frequency
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent extracts and eliminates the conducting wire from the connection path between the lower arm drain and upper arm source. By mounting both transistor chips with their main electrode pads facing the substrate, the connection is achieved directly through the substrate wiring, removing the inductance-causing wire and enabling high-frequency operation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the mounting orientation of transistor chips from the conventional way (with drain pads facing substrate requiring wire connections) to a configuration where both chips are mounted with main electrode pads facing the substrate. This dimensional reconfiguration allows direct substrate wiring connection without intermediate wire bonds, resolving the inductance problem

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If the drain electrode pad of the lower arm transistor and the source electrode pad of the upper arm transistor are connected via conducting wire, then series connection is achieved, but the inductance component causes gate voltage fluctuation

Engineering Contradiction:
Improveseries connection implementationVSAvoidgate voltage stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The conducting wire is extracted from the connection path. The series connection is achieved directly through substrate wiring by mounting both transistor chips with their main electrode pads (drain and source) facing the substrate, eliminating the wire and its inductance that caused gate voltage fluctuation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The substrate wiring pattern serves as an intermediary connection medium between the lower arm drain and upper arm source. Instead of using conducting wires, the substrate's wiring pattern provides a low-inductance path that maintains gate voltage stability while achieving series connection

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9966334B2Semiconductor module
Publication Date: 2018.05.08 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US9966334B2 patent drawing
  • US9966334B2 patent drawing
  • US9966334B2 patent drawing

AI summary

A semiconductor module (10A) according to one embodiment includes: vertical first and second transistor chips (12A, 12B), wherein a second main electrode pad (20) formed on a back surface of the first transistor chip is mounted on and connected to a first wiring pattern (74) on the substrate, a first control electrode pad (16) formed together with a first main electrode pad on a front surface of the first transistor chip is electrically connected to a second wiring pattern (76) on the substrate, third main electrode pad (18) formed together with a second control electrode pad on a front surface of the second transistor is mounted on and connected to the first wiring pattern, and the second control electrode pad (16) formed on a back surface of the second transistor chip is electrically connected to a third wiring pattern.