Semiconductor Module Wiring Inductance for Gate Oscillation
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Solution Overview
Problem
Existing power semiconductor modules with parallel semiconductor switching elements face issues with gate oscillation due to variations in wiring and increased parasitic inductance, leading to power loss and reliability concerns, particularly at high temperatures and under high-frequency operations.
Innovation Solution
The solution involves designing a semiconductor module with a specific wiring configuration where the inductance between control electrode pads is greater than that between main electrode pads, using a common control electrode pattern and pads connected to a drive circuit, to reduce gate oscillation without increasing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a plurality of semiconductor switching elements are operated in parallel to handle large current, then the current handling capability is improved, but parasitic inductance increases due to increased element-disposed area and complicated wiring
Solution Approach 1:
The invention divides the wiring into two separate paths: a first wiring path for main current flow and a second wiring path for control electrode connection. This segmentation allows the main current path to be optimized for low inductance while the control path can be designed separately, reducing the overall parasitic inductance affecting switching characteristics.
Solution Approach 2:
The invention introduces a common connection electrode as an intermediary that connects multiple control electrodes without requiring direct wiring between all control electrodes and the drive circuit. This intermediary structure reduces the complexity and inductance of the control wiring network.
2Reliability
If gate resistance is increased to suppress gate oscillation, then the oscillation is reduced, but switching speed becomes slow and power loss increases
Solution Approach 1:
The invention introduces a common connection electrode as an intermediary that connects multiple control electrodes without requiring direct wiring between all control electrodes and the drive circuit. This intermediary structure reduces the complexity and inductance of the control wiring network.
Solution Approach 2:
The common connection electrode creates an equipotential region that equalizes the potential distribution among multiple control electrodes. This reduces potential differences and oscillations between parallel-connected switching elements without requiring high gate resistance, thereby maintaining fast switching speed while suppressing gate oscillation.
3Power
If the number of parallel semiconductor switching elements is increased, then current handling capability is improved, but gate oscillation occurs due to increased parasitic inductance and wiring variations
Solution Approach 1:
The invention divides the wiring into two separate paths: a first wiring path for main current flow and a second wiring path for control electrode connection. This segmentation allows the main current path to be optimized for low inductance while the control path can be designed separately, reducing the overall parasitic inductance affecting switching characteristics.
Solution Approach 2:
The common connection electrode creates an equipotential region that equalizes the potential distribution among multiple control electrodes. This reduces potential differences and oscillations between parallel-connected switching elements without requiring high gate resistance, thereby maintaining fast switching speed while suppressing gate oscillation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses gate oscillation in parallel-connected semiconductor switching elements, reducing power loss and enhancing reliability across varying temperatures and operational frequencies.
Implementation Method 1
A wiring inductance of a second path formed to extend through the second wires and the control electrode control pattern between the control electrode pads of the plurality of semiconductor switching elements is larger than a wiring inductance of a first path formed to extend through the first wires and the main electrode control pattern between the main electrode pads of the plurality of semiconductor switching elements
Data Source
AI summary
Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.