Semiconductor Memory Device with Mold Layer Openings
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, low power consumption, and high performance due to limitations in the design and fabrication of memory circuits, particularly in the integration of variable resistance elements for efficient data storage.
Innovation Solution
The proposed solution involves a semiconductor device with a specific structure comprising a substrate, mold layers, and conductive material layers, where the mold layers define hole and line openings to create a mesh-type arrangement of contact plugs and conductive lines, enhancing insulation and preventing shorts, thereby improving the resistance characteristics and fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for memory circuits, then the manufacturing process is simpler, but the overlay margin between conductive lines and contact plugs is reduced leading to increased risk of shorts
Solution Approach 1:
The fabrication process is segmented into multiple distinct stages: forming first mold layer with contact holes, forming second mold layer with trenches, and sequential filling operations. This segmentation allows precise control of overlay margins by independently optimizing each layer's positioning without compromising overall process simplicity.
Solution Approach 2:
Mold layers are formed preliminarily before conducting the actual conductive line and contact plug formation. These mold layers pre-establish the geometric constraints and positioning references needed to achieve large overlay margins, preventing shorts before the critical filling step occurs.
2Length of moving object
If miniaturization is pursued in semiconductor devices, then device size is reduced, but manufacturing precision and control over conductive patterns become more difficult
Solution Approach 1:
The patent introduces vertical dimensionality through stacked mold layers (first mold layer and second mold layer at different heights). This multi-dimensional approach allows precise lateral positioning of conductive patterns through vertical stacking, enabling miniaturization while maintaining manufacturing precision through z-axis constraint control.
Solution Approach 2:
Mold layers serve as intermediary structures that mediate between the substrate and the final conductive patterns. These intermediaries provide mechanical support and geometric guidance during miniaturized device fabrication, allowing precise control of conductive pattern dimensions and positions even at reduced device sizes.
3Productivity
If conductive material is filled in all openings simultaneously, then the fabrication process is faster, but shorts between adjacent conductive lines and contact plugs cannot be prevented
Solution Approach 1:
The filling process is segmented into sequential operations: first filling contact holes through the first mold layer, then filling trenches through the second mold layer. This segmentation prevents shorts by ensuring that conductive materials in different regions are formed at different times, eliminating the risk of bridging between adjacent structures during a single filling operation.
Solution Approach 2:
The first mold layer is formed preliminarily to define and protect contact hole regions before trench formation. This preliminary structuring ensures that when trenches are subsequently filled, the contact plugs are already in place and protected, preventing shorts between contact plugs and conductive lines.
Data Source
AI summary
A semiconductor device may include: a substrate; a first mold layer formed over the substrate and comprising a plurality of bottom conductive patterns connected to the substrate; a second mold layer formed over the first mold layer, and defining a plurality of hole openings, wherein each of the hole openings overlaps each of the bottom conductive patterns; a third mold layer formed over the second mold layer, and defining a plurality of line openings, wherein each of the line openings overlaps two or more hole openings of the hole openings; and a conductive material layer buried in the hole openings and the line openings.