Semiconductor Fine Pattern Formation via Mold Mask Segmentation
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in forming fine patterns with reduced design rules, leading to complex and minute contact pad configurations, which are prone to alignment errors and undesired pattern formation during the trimming process due to the strict tolerance requirements of double patterning techniques.
Innovation Solution
A method involving the formation of mold mask patterns and mask spacers on a substrate, followed by a trimming process using gap-fill protection films and mask spacers to expose outermost sidewalls of mold mask patterns, allowing for the etching of conductive lines and contact pads while simplifying the trimming process and reducing the need for complex photolithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technique is used to form fine patterns with reduced design rules, then manufacturing precision is improved, but device complexity increases due to complex mask pattern layout and strict alignment tolerance requirements
Solution Approach 1:
The invention segments the contact pad formation process into two distinct stages: first forming the conductive lines through double patterning, then separately forming contact pads through a simplified trimming process. This segmentation allows each process to be optimized independently, reducing overall complexity while maintaining fine pattern precision.
Solution Approach 2:
The invention extracts the contact pad formation from the conventional integrated process and separates it as an independent trimming process. By taking out the contact pad formation step, the complex mask pattern layout required for simultaneous conductive line and contact pad formation is eliminated, reducing device complexity while preserving manufacturing precision.
2Ease of manufacture
If contact pads are integrally formed with conductive lines using conventional methods, then ease of manufacture is improved, but manufacturing precision deteriorates due to alignment errors and undesired pattern formation
Solution Approach 1:
The invention performs preliminary formation of conductive lines with precise patterns through double patterning before forming contact pads. By establishing the conductive line patterns first with high precision, then adding contact pads through a subsequent trimming process, the method achieves both ease of manufacture and high manufacturing precision without alignment errors.
Solution Approach 2:
The invention introduces a trimming process as an intermediary step between conductive line formation and final device completion. This intermediary trimming process allows precise control of contact pad formation without affecting the previously formed conductive lines, thereby maintaining manufacturing precision while simplifying the overall process.
3Productivity
If design rule is reduced to shrink chip size, then productivity is improved, but manufacturing precision deteriorates due to minute and complicated contact pad configurations
Solution Approach 1:
The invention segments the patterning process to handle reduced design rules effectively. By separating conductive line formation from contact pad formation, each process can be independently optimized for the reduced design rule, maintaining manufacturing precision while enabling chip size reduction and improved productivity.
Solution Approach 2:
The invention changes the process parameters by using a trimming-based approach for contact pad formation instead of conventional photolithography. This parameter change allows precise control of minute contact pad configurations at reduced design rules, maintaining manufacturing precision while enabling smaller chip sizes and higher productivity.
Data Source
AI summary
A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.