Semiconductor Package Mold Path Design

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Solution Overview

Problem

As semiconductor integration density increases, the reduced pitch of pin electrodes on semiconductor chips poses challenges in packaging, including contamination risks and limitations in terminal placement due to exposed inner paths, and thermal expansion coefficient mismatches leading to warpage phenomena.

Innovation Solution

A semiconductor package design featuring a substrate with a mold path including an inner path and a mold hole, where the mold layer extends into the inner path through the mold hole, filling spaces between bumps and encapsulating the semiconductor chip, while the lower plate covers the inner path to prevent contamination and terminal placement issues, and the grooves' configuration helps manage thermal expansion differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the pitch of pin electrodes is reduced to increase integration density, then the number of pins per unit area increases, but contamination risks increase and manufacturing precision becomes more difficult to maintain

Engineering Contradiction:
Improveintegration densityVSAvoidpin pitch control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from planar pin arrangements to three-dimensional bump interconnections, allowing electrodes to connect through vertical vias and multiple layers. This dimensional change enables higher integration density without further reducing the already minimal pin pitch, thereby maintaining manufacturability and precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested interconnection structures where bumps are positioned within recesses of the substrate, and multiple interconnection layers are stacked vertically. This nesting approach allows multiple connection points to occupy overlapping footprints, increasing effective pin density without proportionally increasing contamination risk or manufacturing complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If inner paths are exposed to allow mold layer extension, then packaging efficiency improves, but terminal placement is limited and contamination risk increases

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidcontamination and terminal placement limitations
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the substrate surface into distinct regions: exposed inner paths for mold layer extension, recessed bump areas for electrical interconnection, and protected terminal regions. This segmentation allows each area to serve its specific function without interfering with others, enabling both packaging efficiency and terminal placement flexibility while preventing contamination through proper sealing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces the mold layer as an intermediary substance that fills and seals the exposed inner paths. This mold layer acts as a barrier preventing contamination while allowing the inner paths to remain exposed for packaging efficiency. The bump structures serve as intermediaries between the substrate and semiconductor chip, enabling electrical connection without requiring direct exposure of underlying paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If bumps are used for interconnection to reduce delay, then signal transmission speed improves, but thermal expansion coefficient mismatch causes warpage

Engineering Contradiction:
Improvesignal transmission speedVSAvoidpackage warpage
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The patent applies different material properties to different regions of the package. The bump interconnection structures use materials with thermal expansion coefficients matched to the substrate in critical areas, while other regions use materials optimized for electrical performance. This local quality approach allows fast signal transmission through bumps while maintaining overall package stability and minimizing warpage through strategic material selection in thermally sensitive regions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9397020B2Semiconductor package
Publication Date: 2016.07.19 SAMSUNG ELECTRONICS CO LTD
  • US9397020B2 patent drawing
  • US9397020B2 patent drawing
  • US9397020B2 patent drawing

AI summary

A semiconductor package includes a substrate including a lower plate and an upper plate, a semiconductor chip mounted on a top surface of the substrate, and a mold layer surrounding a sidewall and a bottom surface of the semiconductor chip. The substrate has a mold path including an inner path extending between the lower and upper plates and a mold hole penetrating the upper plate. The mold hole is connected to the inner path. The mold layer extends into the mold path.