Semiconductor Conductive Pattern Fabrication via Mold Segmentation
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Solution Overview
Problem
As semiconductor devices become more highly integrated, there is a need for capacitors with higher capacitance per unit area, which is challenging due to limitations in photolithography processes that restrict the formation of precise and uniform conductive patterns with small feature sizes.
Innovation Solution
A method of fabricating semiconductor devices involves forming multiple mold patterns using sequential photolithography processes to create conductive patterns with high uniformity, overcoming the limitations of minimum pattern pitch by using additional photolithography steps to achieve coplanar top surfaces and precise positioning of mold patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used to form conductive patterns, then manufacturing process is simple, but manufacturing precision deteriorates due to minimum pattern pitch limitation
Solution Approach 1:
The patent divides the single photolithography process into multiple sequential steps: forming a first mold pattern, forming a second mold pattern, and forming a third mold pattern. Each step uses photolithography to create patterns at different stages, allowing the final conductive patterns to achieve precision beyond the limitations of a single photolithography step. This segmentation enables overcoming the minimum pattern pitch limitation while maintaining manufacturing feasibility.
2Manufacturing precision
If additional photolithography steps are added to improve pattern precision, then manufacturing precision improves, but manufacturing time increases
Solution Approach 1:
The patent performs preliminary actions by forming the first mold pattern and second mold pattern before forming the final third mold pattern. Each preliminary pattern serves as a foundation for the next step, ensuring that positioning accuracy is established early and maintained throughout subsequent processing. This preliminary structuring reduces the need for rework and minimizes total process time despite multiple steps.
3Manufacturing precision
If multiple mold patterns are formed to overcome photolithography limitations, then conductive pattern precision improves, but process complexity increases
Solution Approach 1:
The patent implements a nested structure where the first mold pattern, second mold pattern, and third mold pattern are formed sequentially, with each pattern serving as a template for the next. The patterns are nested in the sense that each subsequent pattern is defined relative to the previous ones, creating a hierarchical structure that achieves high precision while organizing the complexity in a systematic, manageable sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of conductive patterns with improved size uniformity and precise positioning, enhancing capacitance density while overcoming the limitations of traditional photolithography in high-density semiconductor devices.
Implementation Method 1
forming a first photoresist pattern, etching the upper mold layer using the first photoresist pattern as an etch mask to form the first upper mold pattern, forming a second photoresist pattern on the additional mold layer, etching the additional mold layer using the second photoresist pattern as an etch mask to form the second upper mold pattern
Implementation Method 2
etching the upper mold layer using the first photoresist pattern as an etch mask to form the first upper mold pattern, etching the additional mold layer using the second photoresist pattern as an etch mask to form the second upper mold pattern, etching the middle mold layer using the first and second upper mold patterns as an etch mask
Data Source
AI summary
A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a substrate, forming a first upper mold pattern and a second upper mold pattern on the middle mold layer to have top surfaces at different levels, etching the middle mold layer using the first and second upper mold patterns as an etch mask to form first and second middle mold patterns, respectively, forming a third middle mold pattern between the first and second middle mold patterns, and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.