Semiconductor Package Molding with Protective Capping
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Solution Overview
Problem
The challenge in manufacturing semiconductor packages is to achieve high performance, high capacity, miniaturization, and light weight while managing contamination sources and maintaining cleanliness in semiconductor manufacturing environments, which is economically and technically demanding.
Innovation Solution
A method involving the manufacturing of semiconductor chips in different environments, where a molding member is formed in a less clean environment and covered with a capping member to prevent contamination, allowing for the formation of a redistribution line layer in a cleaner environment, thereby increasing efficiency and yield without the need for complex equipment or process changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a molding member is formed in a less clean environment, then manufacturing cost and complexity are reduced, but contamination risk increases
Solution Approach 1:
The manufacturing process is segmented into two distinct environments: a first clean environment for manufacturing semiconductor chips and a second less clean environment for forming molding members and assembling packages. This segmentation allows each process to be optimized independently, reducing overall manufacturing complexity and cost while maintaining product quality through controlled interfaces between environments.
Solution Approach 2:
A capping member is introduced as an intermediary component that covers the molding member. This capping member acts as a barrier that prevents contamination from the less clean second environment from reaching the semiconductor chip, thereby enabling the use of a less clean environment for molding while maintaining product cleanliness.
2Productivity
If semiconductor chips are manufactured in a clean environment and then assembled in a less clean environment, then manufacturing efficiency increases, but maintaining cleanliness becomes more difficult
Solution Approach 1:
The capping member is formed in advance during the molding process in the second environment, creating a protective barrier before the packaged device is transferred to the first clean environment for subsequent processing steps such as forming redistribution line layers. This preliminary protective action enables efficient manufacturing in the less clean environment while ensuring cleanliness is maintained for critical processes.
3Manufacturing precision
If redistribution line layers are formed in a clean environment, then product quality is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into segments performed in different environments: molding and assembly in the second less clean environment, and redistribution line layer formation in the first clean environment. The capping member facilitates this segmentation by protecting the chip during transfer and storage, allowing each process segment to be performed in the most appropriate environment without requiring the entire process to occur in a clean room.
Data Source
AI summary
Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.