Semiconductor Mounting Board Capacitor Segmentation
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Solution Overview
Problem
Conventional semiconductor element mounting boards face challenges in reducing impedance and current fluctuation due to longer conductor paths and mismatched inductance and capacitance values of built-in capacitors, which can lead to unstable operation of electronic devices.
Innovation Solution
A semiconductor element mounting board design featuring a laminated insulating structure with strategically placed capacitors and conductor paths, where the first capacitor has lower internal inductance and capacitance compared to the second capacitor, and the first conductor path has smaller inductance than the second, ensuring a reduced impedance and sufficient capacitance for stable current supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If longer conductor paths are used to connect capacitors, then the capacitors can be placed in more positions, but the impedance increases and current supply stability deteriorates
Solution Approach 1:
The patent divides the capacitor system into multiple segments (first capacitor and second capacitor) connected in parallel to the semiconductor element. Each capacitor is connected through separate conductor paths, allowing distributed placement while maintaining low impedance. The segmentation enables flexible positioning of multiple capacitors at different locations on the board without requiring long single conductor paths.
Solution Approach 2:
The patent utilizes the laminated structure of the insulating board to place capacitors in different spatial dimensions and layers. Capacitors can be positioned on different surfaces or within different layers of the board, connected through vertical via holes. This dimensional approach allows short conductor paths while achieving flexible capacitor placement throughout the board structure.
2Quantity of substance
If capacitors with larger capacitance are used, then current supply capability improves, but internal inductance increases and impedance increases
Solution Approach 1:
The patent combines multiple capacitors (first capacitor and second capacitor) in parallel connection to the semiconductor element. This merging approach achieves the desired total capacitance value while each individual capacitor maintains low internal inductance. The parallel combination provides sufficient current supply capability without requiring any single capacitor to have high capacitance that would increase internal inductance.
Solution Approach 2:
The patent optimizes the parameters of individual capacitors by selecting specific capacitance values and corresponding internal inductance characteristics. Rather than using a single large-capacitance component, the design uses multiple capacitors with optimized parameter combinations, where the sum of capacitances meets the current supply requirement while the sum of internal inductances remains low for stable operation.
3Adaptability or versatility
If capacitors are placed farther from the semiconductor element, then layout flexibility improves, but conductor path length increases and current response speed decreases
Solution Approach 1:
The patent segments the capacitor placement into multiple locations around the semiconductor element rather than placing a single capacitor far away. Each segmented capacitor position is connected through its own dedicated conductor path, ensuring that no single path becomes excessively long. This segmentation maintains current response speed while providing layout flexibility.
Solution Approach 2:
The patent utilizes the three-dimensional laminated structure of the insulating board to place capacitors in different layers and positions. By using vertical via holes and multi-layer conductor paths, capacitors can be positioned in spatial dimensions that minimize conductor path lengths while maintaining layout flexibility. This dimensional approach allows capacitors to be placed optimally close to the semiconductor element in the Z-direction while providing horizontal layout flexibility.
Data Source
AI summary
A semiconductor element mounting board includes: a circuit conductor disposed on the insulating board, a plurality of semiconductor element connection pads connected to the circuit conductor, a semiconductor element mounted on a surface of the insulating board, a first capacitor and a second capacitor disposed on a surface or an inside of the insulating board, and a first conductor path configured to connect the first capacitor between the semiconductor element connection pads, and a second conductor path configured to connect the second capacitor between the semiconductor element connection pads; and an inductance of the first conductor path is smaller than an inductance of the second conductor path, and capacitance of the first capacitor is smaller than capacitance of the second capacitor, and an internal inductance of the first capacitor is smaller than an internal inductance of the second capacitor.