Semiconductor Device Multi-Gate Structure Leakage Control
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Solution Overview
Problem
Conventional semiconductor devices face issues with short-channel effects and leakage currents due to poor control over channel current, which affects their electrical performance, and the fin field effect transistor (FinFET) structure does not adequately address these issues.
Innovation Solution
A semiconductor device fabrication method involving a substrate with a first gate structure and source/drain doped layers, a dielectric layer covering the gate structure, a trench exposing the gate structure, a conductive structure in the trench bottom, and an insulation layer in the trench top, where the insulation layer serves as a mask for forming recesses and additional conductive structures, ensuring proper isolation and alignment between conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET structure is used to control channel current, then short-channel effect is reduced, but leakage current still occurs and performance is insufficient
Solution Approach 1:
The patent segments the gate structure into multiple gates (first gate structure and second gate structure) that wrap around the channel from different directions. This multi-gate configuration divides the control function across multiple gate regions, enabling better electrostatic control over the channel and reducing short-channel effects while minimizing leakage current through enhanced channel confinement.
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional wrap-around gate structure. The first gate structure extends in a first direction while the second gate structure extends in a second direction perpendicular to the first direction, creating a multi-dimensional gate configuration that provides superior channel control and reduces leakage current through enhanced electrostatic field distribution.
2Area of stationary object
If conductive structures are placed close together to increase integration density, then device area is reduced, but current leakage between conductive structures increases
Solution Approach 1:
The patent introduces an insulation layer as an intermediary material positioned between the first conductive structure and the second conductive structure. This insulation layer acts as a mediator that electrically isolates the two conductive structures, preventing current leakage while allowing them to be placed in close proximity, thereby maintaining high integration density without sacrificing electrical isolation.
Solution Approach 2:
The patent applies different material properties to different regions: the insulation layer is specifically positioned and sized to provide adequate electrical isolation between conductive structures where needed, while other regions maintain conductive or semiconductor properties. This localized differentiation of material properties enables precise control over current flow paths and minimizes leakage between adjacent conductive structures.
Data Source
AI summary
A semiconductor device and a fabrication method are provided. The method includes providing a substrate; forming a first gate structure and source/drain doped layers over the substrate, where the source/drain doped layers are on both sides of the first gate structure; forming a dielectric layer covering the first gate structure and the source/drain doped layers over the substrate; forming a first trench exposing the first gate structure through the dielectric layer; forming a first conductive structure in the bottom region of the first trench; after forming the first conductive structure, forming an insulation layer in the top region of the first trench; using the insulation layer as a mask, forming recesses on source/drain doped layers through the dielectric layer on both sides of the insulation layer; and forming second conductive structures in the recesses.